研究目的
Proposing a novel scalable digit-serial inverter structure with low space complexity to perform inversion operation in GF(2m) based on a previously modi?ed extended Euclidean algorithm, suitable for constrained implementations of cryptographic primitives in ultra-low power devices.
研究成果
The proposed scalable digit-serial inverter structure achieves significant reductions in area and energy consumption, making it highly suitable for ultra-low power devices with tight restrictions on area and power consumption, despite its lower throughput.
研究不足
The proposed scalable design has significantly lower throughput values compared to other designs, making it less suitable for high-throughput applications.
1：Experimental Design and Method Selection:
The study employs a nonlinear methodology to parallelize the inversion algorithm, focusing on reducing space complexity and improving energy efficiency.
2：Sample Selection and Data Sources:
The research utilizes a modified extended Euclidean algorithm for finite field inversion over GF(2m).
3：List of Experimental Equipment and Materials:
The implementation is verified using Synopsys synthesis tools package version
4：09-SP2 for logic synthesis and power analysis. Experimental Procedures and Operational Workflow:
20 The proposed scalable digit-serial inverter structure is designed, synthesized, and compared with existing designs in terms of area, latency, and critical path delay.
5：Data Analysis Methods:
The performance of the proposed design is evaluated based on area, delay, power, and throughput metrics.
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