摘要： Using parallel associative reduction, iterative re?nement, and conservative early termination detection, we show how to use tree-reduce parallelism to compute correctly rounded ?oating-point sums in Oelog NT depth. Our parallel solution shows how we can continue to exploit the scaling in transistor count to accelerate ?oating-point performance even when clock rates remain ?at. Empirical evidence suggests our iterative algorithm only requires two tree-reduce passes to converge to the accurate sum in virtually all cases. Furthermore, we develop the hardware implementation of two residue-preserving IEEE-754 double-precision ?oating-point adders on a Virtex 6 FPGA that run at the same 250 MHz pipeline speed as a standard adder. One adder creates the residue by truncation, requires only 22 percent more area than the standard adder, and allows us to support directed-rounding modes and to lower the cost of round-to-nearest modes. The second adder creates the residue while directly producing a round-to-nearest sum at 48 percent more area than a standard adder.