研究目的
To present the UFXC32k readout integrated circuit designed for hybrid pixel semiconductor detectors used in X-ray imaging applications, focusing on its design, performance, and characterization.
研究成果
The UFXC32k IC demonstrates excellent performance in terms of offset spread, gain spread, and count rate, making it suitable for high-intensity X-ray imaging applications. Its design allows for high frame rates and efficient signal processing, with potential for further optimization in future iterations.
研究不足
The test system's maximum clock frequency limitation (single date rate clock of 200 MHz) due to the use of NI PXI-6562 Digital Waveform Generator/Analyzer, which restricts the operation of the chip readout with a double data rate clock of 400 MHz as per design specification.
1：Experimental Design and Method Selection:
The UFXC32k IC was designed in a CMOS 130 nm process, featuring a matrix of 128 × 256 pixels with 75 μm pitch, each containing analog and digital blocks for signal processing.
2：Sample Selection and Data Sources:
The chip was bump-bonded to a silicon pixel detector and characterized using X-ray radiation.
3：List of Experimental Equipment and Materials:
NI PXI-6562 Digital Waveform Generator/Analyzer, X-ray generator with a Cu-target, and a crystal monochromator.
4：Experimental Procedures and Operational Workflow:
Measurements included offset, gain, and noise performance, high count rate performance, and frame rate in continuous readout mode.
5：Data Analysis Methods:
Data was analyzed using LabVIEW 2013 for communication protocol and automatic data analysis, with dead time models applied for count rate performance.
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