研究目的
The objective of this work is to demonstrate the real-time DVF capabilities of 5-D in?nite impulse response (IIR) digital ?lters, whose theoretical formulations were established in [7]. To this end, we present an example design and a novel semi-systolic parallel processing hardware implementation and validate the effectiveness of the original DVF algorithm in [7] in ?xed-point for real-time operation.
研究成果
The design and implementation of a novel FPGA-based 5-D depth-velocity ?lter are proposed for real-time LFV processing. The ?lter exploits the concept of MD passive network resonance to obtain a partially separable low-complexity transfer function with three cascaded sections. Each section is mapped into a parallel processing hardware architecture allowing real-time processing of large volume of input data encountered in 5-D LFVs.
研究不足
The limitations include the complexity of implementing 5-D ?lters in real-time due to the large volume of input data and the need for parallel processing architectures to handle the computational load.
