研究目的
Investigating the selective epitaxial growth of GaAs layers on Si (001) substrate with V-grooved trench to reduce the density of crystalline defects.
研究成果
The study demonstrates that a V-grooved Si trench formed by an in situ bake enhances the crystallinity of selectively grown GaAs epitaxial layers by trapping defects at the lower part of the SiO2 sidewall, resulting in larger volumes of defect-free GaAs.
研究不足
The study focuses on the reduction of defects in GaAs layers grown on Si substrates but does not address the integration of these layers into CMOS processes or the potential for Ge diffusion from SiGe buffers.
1：Experimental Design and Method Selection:
The study used the aspect ratio trapping method for selective epitaxial growth of GaAs layers on Si (001) substrate with V-grooved trench. The V-grooved Si surface was formed through a high temperature in situ baking process in H2 atmosphere before GaAs growth in a MOCVD chamber.
2：Sample Selection and Data Sources:
The samples were patterned Si substrates with an opening width of 30 nm, prepared by thermal oxidation, photolithography, and SiO2 etching.
3：List of Experimental Equipment and Materials:
MOCVD (AIXTRON, AIX200/4 RF) was used for GaAs growth, with TMGa and AsH3 as precursors. HR-TEM (JEOL 2100F) and XRD were used for analysis.
4：Experimental Procedures and Operational Workflow:
The substrate was cleaned, baked in situ at high temperature, and then GaAs was grown using a two-step procedure.
5：Data Analysis Methods:
The morphology change and crystalline quality of the GaAs layers were analyzed by HR-TEM and XRD measurements.
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