研究目的
To study the effect of low temperature annealing (80°C) on the transport properties of CIT ?lms to understand the limitations of the lower open circuit potential (Voc) obtained in previous results.
研究成果
Highly crystalline ?lms with only three material peaks were obtained upon heat treatment at 80°C for the sample deposited at ?0.8 V. The samples treated at 80°C for 60 min revealed a reasonable amount of change in the morphological and electrical properties. The current density was found to be increased by two orders of magnitude upon heat treatment as compared to as-deposited samples. The potential barrier was calculated as 0.39 eV and 0.33 eV for as-deposited and heat treated samples deposited at ?0.8 V. The capacitance–voltage measurement showed sharp depletion and accumulation. The maximum built in potential was found to be ~145 mV for as-deposited samples, deposited at ?0.8 V, whereas upon heat treatment it shifted to 210 mV. The depletion width was found to be ~200 nm for the sample deposited at ?0.8 V upon heat treatment. In the present study samples deposited at ?0.8 V showed the optimum results in terms of both materials and transport properties and were found to be suitable for further deposition of solar cell devices.
研究不足
The study is limited to the effect of low temperature annealing (80°C) on the transport properties of CIT ?lms. Further investigation is needed to understand how depletion width and its nature affect the open circuit potential and the overall ef?ciency of a solar cell.