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Hysteresis-Free Hexagonal Boron Nitride Encapsulated 2D Semiconductor Transistors, NMOS and CMOS Inverters

DOI:10.1002/aelm.201800419 期刊:Advanced Electronic Materials 出版年份:2018 更新时间:2025-09-09 09:28:46
摘要: Graphene and subsequently discovered layered semiconducting transition metal dichalcogenides (TMDCs) exhibit numerous exotic physical properties and broad potential device applications. These 2D semiconducting TMDCs have become particularly interesting in next-generation electronic device applications due to their atomic thickness and nonzero bandgap. However, as there is no bulk volume, the 2D nature makes the electronic transport in these crystals highly sensitive to the environmental conditions, such as humidity, adsorbates, and trapped charges in neighboring dielectrics. Due to this environmental sensitivity, 2D-based circuits and devices suffer from a large and undesirable environment-induced hysteresis, which must be eliminated for reliable operation and computation. By mechanically assembling van der Waals (vdWs) heterostructures and edge-contacted graphite electrodes, the 2D semiconducting channel is sealed completely and protected. Here, hexagonal boron nitride (hBN) encapsulated high-performance, hysteresis-free 2D semiconductor transistors, n-type metal-oxide semiconductor, and complementary metal-oxide semiconductor inverters are fabricated. The hBN encapsulation provides excellent protection of semiconducting n-MoS2 and p-WSe2 from environmental factors, resulting in hysteresis-free 2D electronics characteristics that are necessary for the realization of 2D electronics and computing.
作者: Shuai Liu,Kai Yuan,Xiaolong Xu,Ruoyu Yin,Der-Yuh Lin,Yanping Li,Kenji Watanabe,Takashi Taniguchi,Yongqiang Meng,Lun Dai,Yu Ye
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To fabricate hysteresis-free 2D semiconductor transistors, NMOS and CMOS inverters by encapsulating 2D semiconductors with hexagonal boron nitride (hBN) to protect them from environmental factors.

The hBN encapsulated few-layer MoS2 FET exhibited high performance with negligible hysteresis. The integrated NMOS inverter on a single MoS2 flake and CMOS inverter constructed with an n-MoS2 FET and p-WSe2 FET showed negligible hysteresis in the static voltage transfer characteristics. The NMOS inverter exhibited a high voltage gain, while the CMOS inverter exhibited a voltage gain of ≈3 at VDD = 1 V. These hysteresis-free vdWs heterostructures pave the way for 2D logical devices in next-generation electronics and computing.

The limitations include the need for careful and deliberate design of the n- and p-channels’ threshold voltage to improve static power dissipations and the potential for increased voltage gain of the CMOS inverter by optimizing the performance of the p-WSe2 FET.

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