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Single electron transistors with e-beam evaporation of SiO <sub/>2</sub> tunnel barriers

DOI:10.1116/1.5050379 期刊:Journal of Vacuum Science & Technology B 出版年份:2018 更新时间:2025-09-09 09:28:46
摘要: Recent work on fabricating metal-insulator-metal (MIM) single electron transistors (SETs) using deposited dielectrics shows promise for becoming a manufacturable process due to compatibility with modern CMOS processes. This process, the “rib-SET” process [V. Joshi, A. O. Orlov, and G. L. Snider, J. Vac. Sci. Technol. B 26, 2587 (2008); G. Karbasian, A. O. Orlov, and G. L. Snider, J. Vac. Sci. Technol. B 33 (2015)], features a self-aligned island and should allow for scaling SETs below 10 nm. However, one of the biggest roadblocks in realizing a high-quality SET with this process has been dif?culties in developing high-quality, low-noise, MIM tunnel junctions. In this work, the authors report Pt-SiO2-Pt MIM SETs with tunnel barriers deposited by e-beam evaporation as an alternative to atomic layer deposition. There are some challenges in the formation of tunnel barriers via e-beam evaporation that are addressed. It is expected that platinum has a negligible native oxide; however, there is a substantial resistance in as-deposited Pt-SiO2-Pt structures that can be reduced by over 5 orders of magnitude by subjecting the ?nished devices to an anneal in a hydrogen plasma, suggesting the presence of an interfacial platinum oxide. It is shown that this treatment not only increases the conductance through the SET, but that it is necessary for forming high conductance tunnel barriers that are desired for making low-noise SETs.
作者: Matthew J. Filmer,Gregory L. Snider,Alexei O. Orlov
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Investigating the fabrication of metal-insulator-metal (MIM) single electron transistors (SETs) using e-beam evaporation of SiO2 as an alternative to atomic layer deposition for creating tunnel barriers, and addressing the challenges in forming high-quality, low-noise MIM tunnel junctions.

The study demonstrates the successful fabrication of MIM SETs using e-beam deposition of SiO2, overcoming previous challenges with ALD SiO2 on platinum. The hydrogen plasma anneal is crucial for reducing interfacial platinum oxide, leading to high-quality tunnel barriers. The process shows promise for scalable, manufacturable SETs compatible with modern CMOS processes.

The study identifies challenges in forming tunnel barriers via e-beam evaporation, including the presence of an interfacial platinum oxide that requires a hydrogen plasma anneal to reduce. Variations in tunnel barrier film thickness lead to asymmetry in junction conductances, and the actual barrier thickness is much thinner than measured by ellipsometry.

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