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[IEEE 2018 International Wafer Level Packaging Conference (IWLPC) - San Jose, CA, USA (2018.10.23-2018.10.25)] 2018 International Wafer Level Packaging Conference (IWLPC) - Development of Low Temperature Direct Bond Interconnect Technology for Die-To-Wafer and Die-To-Die Applications-Stacking, Yield Improvement, Reliability Assessment

DOI:10.23919/IWLPC.2018.8573278 出版年份:2018 更新时间:2025-09-04 15:30:14
摘要: The Direct Bond Interconnect technology (DBI), commonly referred to as low temperature hybrid bonding, is an attractive bonding technology with the potential of much finer pitch and higher throughput than any solder based microbump bonding. Dielectric bonding takes place at ambient temperatures while the metal interconnection (usually Cu to Cu) forms at low annealing temperatures ranging from 150oC to 300oC. A 6μm pitch process is currently in high volume production for wafer-to-wafer (W2W) hybrid bonding. Die-to-wafer (D2W) and die-to-die (D2D) assembly has been in development at Xperi. The unique challenges include producing shallow, uniform and well controlled Cu recess on Cu bond pads of 5 um or greater, which is substantially larger than what is normally used in W2W bonding and particle minimization on die surface prior to bonding. Xperi-designed daisy chain dies and wafers consist of chains ranging from 2 to 31356 interconnects. Die size is 7.96 mm by 11.96 mm, which is similar to a typical high bandwidth memory (HBM) die. The bonding studies include 10μm and 15μm diameter bond pads on 40μm pitch and 5μm diameter bond pads on 10μm pitch. The die thickness is either 50 μm or 200 μm. In this paper, we present the latest development of our chemical mechanical polish (CMP) technology to produce uniform shallow Cu recess on 15um circular bond pads. The large pad size allows for a relaxed alignment requirement to manufacturing high throughput flip chip bonders available today. Additionally, high volume production ready process for bonding and D2W multi-layer stacking are explored as well as bonding yield and reliability improvement results.
作者: Guilian Gao,Laura Mirkarimi,Thomas Workman,Gabe Guevara,Jeremy Theil,Cyprian Uzoh,Gill Fountain,Bongsub Lee,Pawel Mrozek,Michael Huynh,Rajesh Katkar
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To develop and assess low temperature direct bond interconnect technology for die-to-wafer and die-to-die applications, focusing on stacking, yield improvement, and reliability assessment.

The study successfully demonstrates the development of a low temperature direct bond interconnect technology for D2W and D2D applications, achieving high bonding yields and superior reliability performance. The technology shows promise for next-generation interconnect solutions, with potential applications in high performance computing and automotive electronics.

The study is conducted in a prototype laboratory with manual operation of most equipment, which may not fully replicate high volume production conditions. The alignment accuracy requirements for smaller bond pads may limit the applicability of current flip chip bonders.

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