研究目的
Investigating the use of digital logic and DC negative feedback in frequency doublers to suppress unwanted harmonics in millimeter-wave systems.
研究成果
The study demonstrates broadband frequency doublers with excellent suppression of spurious harmonics and low phase noise, offering flexibility in designing frequency multiplier chains with relaxed filter requirements. This is particularly beneficial for monolithic designs where on-wafer filters are large and have poor out-of-band rejection.
研究不足
The performance of the doublers at input frequencies higher than 26.5 GHz was not tested due to available test equipment limitations. Additionally, the harmonic rejection at such frequencies remains untested.
1：Experimental Design and Method Selection:
The study employs digital logic and DC negative feedback in frequency doublers to suppress spurious harmonics. The design includes input/output buffer stages based on emitter-coupled logic (ECL) gates, an XOR gate, and feedback-controlled delay circuits.
2：Sample Selection and Data Sources:
The ICs were characterized on-wafer, with measurements conducted using a Rohde & Schwarz FSU spectrum analyzer, an OML harmonic mixer, and a Quinstar double balanced mixer.
3：List of Experimental Equipment and Materials:
The ICs were designed into a 130 nm InP HBT process, utilizing 50 ?/square thin film resistors, 0.3 fF/μm2 MIM capacitors, and three-levels of gold interconnections.
4：3 fF/μm2 MIM capacitors, and three-levels of gold interconnections.
Experimental Procedures and Operational Workflow:
4. Experimental Procedures and Operational Workflow: The doublers were tested for output power and harmonic rejection over specified frequency ranges, with losses of cables and probes de-embedded.
5：Data Analysis Methods:
Output powers and harmonic rejections were measured and compared with simulations to evaluate performance.
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