摘要： An ultra-low-jitter, ring-LC-hybrid injection-locked clock multiplier (ILCM) is presented to achieve a high multiplication factor of 114. The proposed hybrid ILCM cascades a ring-type voltage-controlled oscillator (VCO)-based ILCM and an LC-type VCO-based ILCM. Using a dual-purpose frequency calibrator (DPFC) that can continuously calibrate the frequency drifts of the two VCOs, concurrently, the proposed ILCM can maintain excellent jitter performance against process-voltage-temperature (PVT) variations. Since the DPFC eliminates the use of an additional calibrator and operates at a very low frequency, it can reduce the expenditures for silicon and power. The proposed ILCM was fabricated in a 65-nm CMOS process. The RMS jitter of the 22.8-GHz output, integrated from 1 kHz to 100 MHz, was 153 fs, and the DPFC restricted its variations due to variations in temperatures and supply voltages to less than 180 fs. The proposed ILCM achieved the power efficiency of 0.32 mW/GHz. The active area was 0.2 mm2. The total power consumption was 7.4 mW, but the DPFC consumed only 400 μW.