摘要： With the significant reduction in board space occupied by the smaller GaN transistors, topologies that require a greater number of active devices as a tradeoff for reduced passive size, the main barrier to higher density, have become attractive. Switched capacitor multilevel converters are good examples of topologies that can effectively reduce or eliminate passive components. Two GaN based proof-of-concept designs (three-level converters), one for a low voltage (LV) 48 V server application and the other for a higher voltage (HV) 400 V power factor correction (PFC) circuit are discussed in this paper. As a result of using lower figure-of-merit (FOM) devices, significant efficiency gains are observed for the LV and HV converters developed in this paper compared to a two-level topology. Smaller passive size (mainly inductors) also provides a significant increase in power density for the LV converter. A startup scheme is discussed which eliminates the need for extraneous control loops or high voltage rated devices for the top switch. Finally, an electrical performance comparison is also shown for a two-stage intermediate bus architecture (IBA) developed with the GaN based three-level converter for the front end and a high frequency GaN-based second buck stage for 48 V to 1 V point-of-load (PoL) conversion. Two choices of intermediate bus voltage are investigated: 12 V and 6 V. Each bus voltage demonstrates its advantage in a certain range of load current.