研究目的
To develop a new high-speed readout system for silicon on insulator (SOI) pixel detectors to overcome the limitations of obsolete FPGA boards and achieve higher performance for experiments requiring high-speed imaging.
研究成果
The new DAQ system using the KC705 board achieved a throughput of 95.3 fps in continuous mode and 762.5 fps in maximum-speed mode for the INTPIX4 detector, demonstrating improved performance over previous systems. However, further debugging is needed to address limitations in the DDR_IO module for full functionality.
研究不足
The prototype DAQ system has an experimental DDR_IO module with incomplete functions, limiting capacity to 256 MB and causing issues in maximum-speed mode. ADC control was not fully implemented, requiring the use of dummy data for testing.
1：Experimental Design and Method Selection:
The study involved designing a new data acquisition (DAQ) system using the KC705 evaluation board with a Kintex-7 FPGA to replace the outdated SEABAS2 board. The design focused on maintaining backward compatibility with existing resources and improving throughput for high-speed imaging.
2：Sample Selection and Data Sources:
The INTPIX4 SOI pixel detector was used as the provisional target, with dummy data employed for testing due to ADC control being under implementation.
3：List of Experimental Equipment and Materials:
Equipment included the KC705 evaluation board, ADC/DAC/NIM sub-board, INTPIX4 detector, and a DAQ PC with specified components.
4：Experimental Procedures and Operational Workflow:
The system was tested under three conditions to assess interframe period stability: continuous data-taking without DDR_IO module, with DDR_IO module, and at eight times faster operation. Measurements were made using a counting circuit with a 200-MHz reference clock.
5：Data Analysis Methods:
Interframe periods were measured and analyzed for stability, with results plotted to evaluate performance in terms of frame rates and throughput.
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