研究目的
To suppress kink effect and improve electrical reliability in poly-Si thin film transistors through asymmetric dual channel design.
研究成果
Asymmetric dual channel length poly-Si TFT (ADCL) effectively suppresses kink currents and improves reliability under hot carrier stress by inducing a high voltage at the floating node, reducing impact ionization and transconductance degradation. ADCL performs better than asymmetric dual channel width (ADCW) for the same W/L ratio. The findings provide a useful design approach for reliable poly-Si TFTs without additional fabrication steps.
研究不足
The study is limited to specific TFT designs on glass substrates and may not generalize to other materials or structures. The asymmetry in channel length or width requires careful design to avoid kink breakdown in sub-TFT1 under high voltage, and the methods may not fully eliminate all reliability issues. Optimization for different applications or scaling is not addressed.
1：Experimental Design and Method Selection:
The study involved designing and fabricating asymmetric dual channel (ADC) poly-Si TFTs with variations in channel length and width to suppress kink currents and improve reliability under hot carrier stress. Technology computer-aided design (TCAD) simulation was used to analyze internal behaviors, employing Selberherr's impact ionization model and density of state (DOS) calibration.
2：Sample Selection and Data Sources:
N-type self-aligned poly-Si TFTs were fabricated on glass substrates. Samples included single-TFT (ST), symmetric dual channel TFT (SDC), symmetric dual channel TFT with wide channel-width (SDC-W), asymmetric dual channel length (ADCL), and asymmetric dual channel width (ADCW) TFTs, with specific dimensions defined for group-L (channel length variations) and group-W (channel width variations).
3：List of Experimental Equipment and Materials:
Equipment included plasma enhanced chemical vapor deposition (PECVD) for a-Si deposition, excimer laser annealing (ELA) system for crystallization, ion shower doping system for source/drain formation, and optical microscope for imaging. Materials included glass substrates, silicon dioxide buffer layer, a-Si, gate dielectric, metal layers, and inter-layer dielectric.
4：Experimental Procedures and Operational Workflow:
Fabrication steps involved depositing 100-nm thick a-Si by PECVD, performing pulsed ELA for crystallization, patterning poly-Si islands, depositing gate dielectric and metal, ion shower doping for source/drain regions, depositing inter-layer dielectric, patterning contact holes, and depositing source/drain metal. Electrical measurements included drain current (IDS) vs. drain voltage (VD) characteristics, leakage current measurements, and transconductance degradation under hot carrier stress (VGS = VTH + 4 V, VDS = 13 V). TCAD simulations were conducted to analyze floating node voltage, electric field, and hole concentration.
5：Data Analysis Methods:
Data from electrical measurements were analyzed to compare kink current suppression and reliability. TCAD simulation results were used to interpret physical parameters such as maximum electric field and hole concentration, with statistical comparisons made between different TFT structures.
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