研究目的
Investigating the influence of lateral electric fields on charge trapping and detrapping dynamics at the interface between MoS2 and SiO2 layers in field-effect transistors.
研究成果
The research demonstrated that lateral electric fields from VDS can modulate charge trapping at the MoS2/SiO2 interface, with trapping occurring at lower VDS ranges and detrapping at higher ranges (above 110 V). Inserting an h-BN layer improved interface quality, eliminated hysteresis, and enhanced carrier mobility, providing stable electrical characteristics. This offers insights into controlling interface-trapped carriers in 2D material-based transistors for better device performance.
研究不足
The study used MoS2 films of different thicknesses for comparisons, which may affect the accuracy of thickness-dependent charge trapping analysis. The high VDS required for detrapping (over 105 V) could lead to device degradation or breakdown. The experiments were conducted under vacuum conditions, which may not represent real-world ambient environments.
1：Experimental Design and Method Selection:
The study involved fabricating MoS2 FETs with and without an h-BN buffer layer to investigate charge trapping effects. Electrical characterizations were performed using multiple VDS sweeps to observe trapping and detrapping processes under lateral electric fields. The Poole-Frenkel model was used to analyze trap energy levels.
2：Sample Selection and Data Sources:
Multilayer MoS2 films were mechanically exfoliated from bulk crystals and transferred onto SiO2/Si substrates. Samples included MoS2 FETs with varying thicknesses and those with an inserted h-BN layer.
3：List of Experimental Equipment and Materials:
Equipment included a micro-manipulator system (AP-4200GP, UNITEK) for transfer, electron beam lithography system (JSM-6510, JEOL) for patterning, electron beam evaporator (KVE-2004L, Korea Vacuum Tech.) for electrode deposition, semiconductor parameter analyzer (Keithley 4200-SCS) for electrical measurements, and Raman spectrometer (XperRam 200, Nanobase, Inc.) for material characterization. Materials included MoS2, h-BN, PMMA 950 K, Ti, Au, and SiO2/Si substrates.
4：Experimental Procedures and Operational Workflow:
MoS2 films were exfoliated and transferred. For FETs with h-BN, MoS2 was transferred onto h-BN using a micro-manipulator, followed by annealing. Electrodes were patterned using electron beam lithography and deposited with Ti/Au. Electrical measurements were conducted in vacuum, applying VGS,before pulses and multiple VDS sweeps to study trapping effects.
5：Data Analysis Methods:
Carrier mobility was calculated using the formula μ = (dIDS / dVGS) × [L / (WCiVDS)]. Saturation currents were analyzed to infer trapping and detrapping behaviors. The Poole-Frenkel model was applied to estimate trap energy levels.
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