研究目的
To examine and characterize a fabricated gate-driver in a class-E resonant inverter for driving self-oscillating gallium nitride and logic-level power transistors, focusing on the implications of an ESD diode and its parasitic capacitance.
研究成果
The fabricated gate-driver ASIC is effective for driving self-oscillating GaNFETs and logic-level power transistors. The parasitic capacitance of the ESD diode (56.7 pF) is negligible and does not impair performance. The diode clamps the output voltage to a minimum of -2 V, but this does not alter the basic functionality. Simulations and measurements show deviations of 5-18%, attributable to component tolerances and modeling inaccuracies, confirming the ASIC's usability in start-up conditions for resonant converters.
研究不足
The study has limitations such as discrepancies between simulation models and actual circuitry, unmodeled resistances in components leading to faster oscillation decay in measurements, and component tolerances causing deviations in results. The ESD diode introduces substrate currents and clamps output voltage, which may affect performance in some applications.
1：Experimental Design and Method Selection:
The study involves designing and fabricating an ASIC gate-driver in a 180 nm process, including high-voltage transistors, CMOS gate-drivers, a level-shifter, and reset circuitry. A prototype PCB is used for testing. Methods include simulation (e.g., LTSpice) and laboratory measurements to assess parasitic capacitance and functional behavior.
2：Sample Selection and Data Sources:
The test die is fabricated and packaged in a 64-pin QFN package. Data is sourced from simulations of the parasitic extracted layout and experimental measurements using an oscilloscope.
3：List of Experimental Equipment and Materials:
Equipment includes a Lecroy Waverunner 620Zi oscilloscope, power supplies, and components like resistors, inductors, and capacitors for the LC-tank load. Materials include the fabricated IC and PCB.
4：Experimental Procedures and Operational Workflow:
Procedures involve estimating parasitic capacitance by discharging it through a load resistor and measuring the time constant. Functional validation uses an LC-tank load to simulate self-oscillating behavior. Measurements are taken of voltages at nodes A and B under different conditions.
5：Data Analysis Methods:
Data analysis includes calculating parasitic capacitance from discharge time constants, comparing simulation and measurement results, and assessing deviations using tolerances and theoretical models.
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