研究目的
To perform failure analysis on 1.2-kV planar SiC MOSFETs degraded under single-stress short circuit operations at high temperatures and nominal voltage to understand the root cause of the gate-oxide degradation mechanism.
研究成果
The gate reliability in planar SiC MOSFETs is compromised by high junction temperature and high bias voltage during short-circuit events, leading to cracks in the dielectric, metal particles, and alterations in the source metallization, which increase gate and drain leakage currents. Bias voltage plays a significant role beyond just critical energy in causing degradation.
研究不足
The study is limited to planar SiC MOSFETs and specific test conditions; it does not cover trench structures or other device types. Material analysis of particles was not performed, and the root cause of cracks is not fully understood. The experiments were stopped before complete gate breakdown to allow for physical analysis, which may not capture full failure modes.
1：Experimental Design and Method Selection:
The study involves short-circuit testing of SiC MOSFETs under varying DC-link voltages and initial junction temperatures, followed by failure analysis using techniques like Focused-Ion Beam (FIB) and Scanning Electron Microscopy (SEM) to compare degraded and new devices.
2：Sample Selection and Data Sources:
Commercial
3：2-kV/90-A SiC MOSFETs (C2M0025120D) in TO-247 packages were used as samples. List of Experimental Equipment and Materials:
Equipment includes a Focused-Ion Beam system, InGaAs infra-red camera, and standard electrical test setups for short-circuit experiments. Materials include the SiC MOSFET devices.
4：Experimental Procedures and Operational Workflow:
Short-circuit tests were conducted with increasing pulse durations at different bias voltages (400 V and 600 V) and junction temperatures (25°C and 150°C). After degradation, the package was removed, and hot spots were located using an infra-red camera. FIB cuts were performed to analyze structural changes.
5：Data Analysis Methods:
Electrical waveforms (drain voltage, drain current, gate-source voltage) were analyzed to observe degradation. Structural images from FIB and SEM were compared between new and degraded devices to identify defects.
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