研究目的
To present the hardware implementation of a stand-alone Electrical Capacitance Tomography (ECT) system using FPGA for imaging conductive materials, specifically monitoring molten metal in the Lost Foam Casting process, with a focus on achieving high performance in speed and design density.
研究成果
The FPGA-based ECT system successfully achieves high performance with improved speed and reduced size compared to PC-based systems. It uses only 11% of FPGA logic elements and 15% memory, with low power consumption (12 mW). The proposed architecture is efficient for real-time applications, demonstrating accurate image reconstruction for metal distributions in the Lost Foam Casting process. Future work could explore enhancements in precision and scalability.
研究不足
The system is designed for specific applications like imaging conductive materials in casting processes; it may not generalize to other tomography types. The use of fixed-point arithmetic limits precision for very large or tiny numbers. The hardware design is complex and requires specialized tools and expertise. Synchronization issues with VGA interface and memory access could affect performance. The study does not address scalability to larger sensor arrays or higher resolutions.
1：Experimental Design and Method Selection:
The study employs a hardware-software codesign approach using FPGA (Altera Cyclone V SoC) for implementing the ECT system. A reconfigurable segmented parallel inner product architecture is proposed for matrix multiplication in image reconstruction algorithms like Iterative Linear Back Projection (ILBP). Finite Element Method (FEM) is used for sensitivity matrix calculation.
2：Sample Selection and Data Sources:
The system uses six capacitance sensors mounted around a rectangular foam pattern in a circular flask to simulate the Lost Foam Casting process. Capacitance measurements are collected wirelessly from sensors.
3：List of Experimental Equipment and Materials:
Includes capacitive sensors, wireless nodes (Mote technology, Crossbow MIB600CA gateway, MicaZ mote), FPGA module (Altera Cyclone V 5CSXFC6D6F31C6), SDRAM memory, VGA peripheral, Ethernet interface, and development tools (Matlab HDL Coder, Altera Quartus II, SoC EDS).
4：Experimental Procedures and Operational Workflow:
Steps involve configuring hardware with Qsys, writing HDL files with Quartus, deploying software on ARM processor, collecting capacitance data wirelessly, applying ILBP algorithm for image reconstruction, and displaying images via VGA.
5：Data Analysis Methods:
Performance is evaluated based on FPGA resource usage (logic elements, memory), propagation delay, power consumption, and accuracy of reconstructed images compared to actual metal distributions.
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