- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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[IEEE 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Rome, Italy (2019.6.17-2019.6.20)] 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Technological Features of Graphene-based RF NEMS Capacitive Switches on a Semi-insulating Substrate
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： sub-sampling,analog-to-digital converter (ADC),voltage-domain,All-digital phase-locked loop (AD-PLL),frequency synthesizer,CMOS,low-power
更新于2025-09-19 17:13:59
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[IEEE 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Rome, Italy (2019.6.17-2019.6.20)] 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - A Compact Octa-band Antenna for Handsets Application
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： sub-sampling,analog-to-digital converter (ADC),voltage-domain,All-digital phase-locked loop (AD-PLL),frequency synthesizer,CMOS,low-power
更新于2025-09-19 17:13:59
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[IEEE 2018 Fifth International Conference on Millimeter-Wave and Terahertz Technologies (MMWaTT) - Tehran, Iran (2018.12.18-2018.12.20)] 2018 Fifth International Conference on Millimeter-Wave and Terahertz Technologies (MMWaTT) - MMWaTT 2018 Organizing Committee
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： frequency synthesizer,sub-sampling,CMOS,voltage-domain,analog-to-digital converter (ADC),All-digital phase-locked loop (AD-PLL),low-power
更新于2025-09-19 17:13:59
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[IEEE 2019 Photonics North (PN) - Quebec City, QC, Canada (2019.5.21-2019.5.23)] 2019 Photonics North (PN) - Differences between foetal and adult meniscus and cartilage revealed by Polarization Second Harmonic Generation Microscopy
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： analog-to-digital converter (ADC),All-digital phase-locked loop (AD-PLL),voltage-domain,sub-sampling,frequency synthesizer,low-power,CMOS
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE International Symposium on Phased Array System & Technology (PAST) - Waltham, MA, USA (2019.10.15-2019.10.18)] 2019 IEEE International Symposium on Phased Array System & Technology (PAST) - A Low Profile Tightly Coupled Antenna Array with 80?° Scanning for Multifunctional Applications
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： sub-sampling,analog-to-digital converter (ADC),voltage-domain,All-digital phase-locked loop (AD-PLL),frequency synthesizer,CMOS,low-power
更新于2025-09-19 17:13:59