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[IEEE 2018 IEEE International Conference on Semiconductor Electronics (ICSE) - Kuala Lumpur (2018.8.15-2018.8.17)] 2018 IEEE International Conference on Semiconductor Electronics (ICSE) - Challenges in Developing Thin Profile, Smaller Flip Chip Bump Pitch FCBGA Packaging
摘要： The influence of substrate copper density distribution, substrate bump coplanarity, stiffener attach process, and substrate clamping by magnetic boat during die attach were evaluated. The substrate warpage behavior throughout the package assembly process was characterized using shadow moiré. Balanced substrate copper density distribution, pre-stiffener substrate before flip chip bump reflow, and substrate clamping during reflow reduced flip chip solder bridging fall-out. The decrease in solder bridging was due to the lower substrate warpage seen during die attach. In particular, solder bridging fall-out was well-correlated to die attach area warpage. Substrate with and without clamping during reflow has met the package reliability requirement.
关键词： Substrate Warpage,FCBGA,Smaller Pitch,Flip Chip Bump Solder Bridging
更新于2025-09-23 15:22:29
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[IEEE 2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition - Warsaw (2017.9.10-2017.9.13)] 2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition - High voltage WireLED powered directly by mains 230 Volts
摘要： for the need of energy saving, LEDs are taking more and more space in lighting modules. Moreover, LEDs add several applications to the lighting function, smartness, dimming, bio photonic applications, a lot of fields that none former light sources could reach [1]. The manufacturers of course must keep the target of making a device compatible with the standards in terms of safety first, but moreover the compactness and reliability with the well-known thermal issues, depending on the wall plug efficiency of the component. In order to manage all the mentioned points, as often, packaging is the key point if one seeks to maximize the lifetime of a LED based luminaire. Indeed, because they are aware of the existing technologies and comparison thanks to quick information available on the Internet, today’s customers cannot accept to pay a more expensive light source that have lower performance than the former lighting technologies [2]. The paper that we propose describes the manufacturing and the packaging of a LED device made from GaN micro wires compatible with direct mains powering on the 230 Volts-50 Hz network. We show why the heterogeneous stack to manufacture the lighting device, coupled with the high voltage input is a big challenge. Once the front side wire LEDs patterning is finished, many technological steps remain in order to deliver a WLP assembly ready for the back-end assembly process. The carrier bonding, the back side processing for N and P contacts patterning, the hybridization by flip chip technology using copper bumps or solder balls are roughly described with the related issues. Final thermal and electrical characterizations were conducted to evaluate the performances of the high voltage LED device.
关键词： High voltage,Packaging,Bump,WireLED,IMS,Flip Chip,Trench
更新于2025-09-12 10:27:22
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Development and optimization of the laser-assisted bonding process for a flip chip package
摘要： In a ?ne pitch ?ip chip package, a laser-assisted bonding (LAB) technology has recently been developed to overcome several reliability and throughput issues in the conventional mass re?ow (MR) and thermal compression bonding technology. This study investigated the LAB process for a ?ip chip package with a copper (Cu) pillar bump using numerical heat transfer and thermo-mechanical analysis. During the LAB process, the temperature of the silicon die was uniform across the entire surface and increased to 280 (cid:3)C within a few seconds; this was high enough to melt the solder. The heat in the die was quickly conducted to the substrate through the Cu pillar bumps. Meanwhile, the substrate temperature was low and remained constant. Therefore, a stable solder interconnection was quickly achieved with minimal stress and thermal damage to the package. The substrate thickness, the number of Cu bumps, and the bonding stage temperature were found to be important factors affecting the heat transfer behavior of the package. The temperature of the die decreased when a thinner substrate, a higher number of Cu bumps, and a lower bonding stage temperature were used. If the temperature of the die was not suf?ciently high, insuf?cient heat was transferred to the solder to melt it, resulting in incomplete solder joint formation. Thermo-mechanical analysis also showed that the LAB process produced lower warpage and thermo-mechanical strain than the conventional MR process. These results indicated that a LAB process using a selective local heating method would be bene?cial in reducing thermo-mechanical stress and increasing throughput for the ?ne pitch ?ip chip packages.
关键词： Laser-assisted bonding,Copper pillar bump,Thermo-mechanical analysis,Flip chip package,Heat transfer
更新于2025-09-11 14:15:04