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- 2018
- contrast stretch
- CMOS image sensor
- point-of-care (POC) diagnosis
- bio-microfluidic imaging
- Optoelectronic Information Science and Engineering
- Xi’an University of Technology
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A 2.6 μW Monolithic CMOS Photoplethysmographic (PPG) Sensor Operating with 2 μW LED Power for Continuous Health Monitoring
摘要: Photoplethysmography (PPG) enables wearable vitals monitoring. Nevertheless, it is still limited by the few mA of the LEDs driving current. We present a PPG sensor integrating an array of dedicated pinned-photodiodes (PPD) with a full readout chain integrated in a 0.18 μm CMOS Image Sensor (CIS) process. The sensor features a total input referred noise of 0.68 e?rms per PPD, independently of the input light, and achieves a 4.6 μW total power consumption, including the 2 μW LED power, at 1.38 bpm heart rate average error.
关键词: CMOS,wearable,CIS,PPG,low-power,low-noise,LED,Array,PPD,Photodetector
更新于2025-09-11 14:15:04
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[IEEE 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Munich, Germany (2019.6.23-2019.6.27)] 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Bi-Junction Carrier Depletion Type Electro-Optic Phase-Shifters
摘要: Silicon photonic integrated circuits (PICs) combine dense optical system integration with industrial scalability by adopting well-established CMOS fabrication processes. An electro-optic phaseshifter (EOP) represents a basic building unit of several PICs applications, including datacom optical switches, PIC-FPGAs, and beam steering. In-situ resistive-heaters in close vicinity of waveguides, or free-carrier injection/depletion in doped junctions, are common methods to build EOPs. Literature reports thermal shifters consuming 24.7 mW to achieve DC large signal π-phaseshift, power consumption of injection PIN implementations and depletion PN modulators of 10 mW and ≈ 0 mW respectively. A thermal EOP naturally avoids carrier-induced optical insertion losses (IL), in contrast to a PIN/PN modulator. Thus, thermal and PIN/PN methods trade-off IL with electrical power rather than minimizing both. An EOP of low optical losses and low electrical power is highly desired in large-signal, and low-speed applications.
关键词: electro-optic phaseshifter,datacom optical switches,PIC-FPGAs,beam steering,CMOS fabrication,Silicon photonic integrated circuits
更新于2025-09-11 14:15:04
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Wearable SiPM-based NIRS Interface Integrated with Pulsed Laser Source
摘要: We present the design of a miniaturized probe integrating silicon photomultiplier and light-pulsing electronics in a single 2x2mm2 CMOS chip which includes functional blocks such as a fast pulse-laser driver and synchronized single-photon detection circuit. The photon pulses can be either counted on-chip or processed by an external high-speed electronic module such as time-corelated single photon counting (TCSPC) unit. The integrated circuit was assembled on a printed circuit board (PCB) and also on a 2.5D silicon interposer platform of size 1 cm and interfaced with a silicon photomultiplier (SiPM), vertical cavity surface emitting laser (VCSEL) and other ancillary components such as capacitors and resistors. Our approach of integrating an optical interface to optimize light collection on the small active area and light emission from the vertical-cavity surface-emitting laser (VSCEL) will facilitate clinical adoption in many applications and change the landscape of Near Infrared Spectroscopy (NIRS) hardware commercially due to significant optode-size reduction and the elimination of optical fibers.
关键词: Near-Infrared Spectroscopy (NIRS),Time-Domain (TD),complementary metal-oxide-semiconductor (CMOS),Vertical Cavity Surface Emitting Laser (VCSEL),Silicon Photomultiplier (SiPM),Optical Probe
更新于2025-09-11 14:15:04
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[IEEE 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Udine, Italy (2019.9.4-2019.9.6)] 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - ATOMOS: An ATomistic MOdelling Solver for dissipative DFT transport in ultra-scaled HfS <sub/>2</sub> and Black phosphorus MOSFETs
摘要: A state-of-the-art DFT-NEGF based ATOmistic - MOdelling Solver (ATOMOS) was developed and used to assess the physics and fundamental-performance potential of various scaled mono-layer transition-metal-dichalcogenides and black- phosphorus (BP) MOSFETs down to a gate length of 5 nm, including the effect of electron-phonon scattering. Our study highlights the good scalability and drive-current potential of HfS2 and the impact of optical-phonon scattering for BP.
关键词: DFT NEGF,CMOS,2D-material,Semiconductor Physics,Quantum transport
更新于2025-09-11 14:15:04
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[IEEE 2019 IEEE Photonics Conference (IPC) - San Antonio, TX, USA (2019.9.29-2019.10.3)] 2019 IEEE Photonics Conference (IPC) - CMOS Compatible Dual Avalanche Photodiode for Algorithmic Visible Spectral Sensing
摘要: A previously reported CMOS-compatible dual avalanche photodiode design is exploited to develop a maximum-likelihood spectral-sensing algorithm, which maps the dual photocurrents to the light’s wavelength. Optimization over the reverse biases of the two APDs yields a spectral resolution of 10 nm within 440-650 nm.
关键词: spectral sensing,maximum likelihood,smart lighting,Avalanche photodiode,silicon,dual APD,CMOS
更新于2025-09-11 14:15:04
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[IEEE 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Qingdao (2018.10.31-2018.11.3)] 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Orientation controlled GaSb nanowires: from growth to application
摘要: In recent years, high-mobility GaSb nanowires have received tremendous attention for high-performance p-type transistors; however, due to the difficulty in achieving thin, uniform and orientation-controlled nanowires (NWs), there is limited report until now addressing their orientation-dependent properties in this important one-dimensional material system, where all these are essential information for the deployment of applications. Using various GaSb NWs CMOS-compatible Pd catalysts, we demonstrated the formation of high-mobility (cid:1766)111(cid:1767)-oriented GaSb nanowires (NWs) via vapor-solid-solid (VSS) growth by the newly developed surfactant-assisted chemical vapor deposition through a complementary experimental and theoretical approach. In contrast to NWs formed by the conventional vapor-liquid-solid (VLS) mechanism, cylindrical-shaped Pd5Ga4 catalytic seeds were present in solid catalysts, our Pd-catalyzed VSS-NWs. As stoichiometric Pd5Ga4 was found to have the lowest crystal surface energy and thus giving rise to a minimal surface diffusion as well as an optimal in-plane interface interface for efficient orientation at epitaxial NW nucleation. Over 95% high crystalline quality NWs were grown in (cid:1766)111(cid:1767) orientation for a wide diameter range of between 10 and 70 nm. Back-gated the field-effect Pd-catalyzed GaSb NWs exhibit a superior peak hole mobility of ~330 cm2 V-1 s-1, close to the mobility limit for a NW channel diameter of ~30 nm with a free carrier concentration of ~1018 cm-3. This suggests that the NWs have excellent homogeneity in phase purity, growth orientation, electrical characteristics. Contact printing process was also used to fabricate large-scale assembly of Pd-catalyzed GaSb NW parallel arrays, confirming the potential constructions and applications of these high-performance electronic devices.
关键词: vapor-solid-solid growth,GaSb nanowires,high-mobility,CMOS-compatible,orientation-controlled
更新于2025-09-11 14:15:04
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[IEEE 2019 16th International Symposium on Wireless Communication Systems (ISWCS) - Oulu, Finland (2019.8.27-2019.8.30)] 2019 16th International Symposium on Wireless Communication Systems (ISWCS) - A Differential Reflection-Type Phase Shifter Based on CPW Coupled-Line Coupler in 45nm CMOS SOI
摘要: This paper presents a mm-wave fully differential coplanar waveguide (CPW) vertically-coupled lines coupler and a reflection type phase shifter (RTPS) based on the proposed coupler. The use of grounded strip line structure for vertical coupling in CPW based coupler provides not only the improved coupling properties than the edge coupling but also provides the opportunity of using surrounding area efficiently to reduce area. The proposed coupler and phase shifter are designed and fabricated in 45nm CMOS SOI technology. Measured insertion loss of the coupler is ~ 6 dB from 18 to 43 GHz. A digitally controlled parallel LC load is used for controlling the phase of the phase shifter. Measured phase tuning range is 115 degrees, with insertion loss variation of 4.5 to 9 dB, for a frequency range of 39 GHz to 45 GHz. Total drawn area of the phase shifter is 0.214 mm2. The area of the proposed RTPS is smaller than the recently published state-of-the-art structures.
关键词: 5G,mmWave,Phased Array,Hybrid Coupler,Phase shifter,CMOS SOI
更新于2025-09-11 14:15:04
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[IEEE 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) - Dallas, TX, USA (2019.8.4-2019.8.7)] 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) - Rapid Simulation of Photonic Integrated Circuits using Verilog-A Compact Models
摘要: With the advent of silicon-based integration of photonics, there is a growing interest in the electronic circuits community to develop hybrid electronic-photonic integrated systems. However, photonic integrated circuits (PICs) design tools have focused on the solutions of Maxwell’s equations using numerical methods. Recently developed PIC system-level design tools employ s-parameter modeling of optical components. in such platforms, accurate modeling of electronic However, driver and interface circuits is not supported. To allow electronic integrated circuit (IC)-centric design, there is a trend of compact modeling of photonic components using Verilog-A so that they can be co-simulated with CMOS electronics. In this work, we present our modeling approach and a novel method for rapid frequency-domain simulation of PICs.
关键词: Ring resonators,Verilog-A,Silicon Photonics (SiP),CMOS photonics,Photonic integrated circuits (PICs)
更新于2025-09-11 14:15:04
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[IEEE 2019 IEEE Energy Conversion Congress and Exposition (ECCE) - Baltimore, MD, USA (2019.9.29-2019.10.3)] 2019 IEEE Energy Conversion Congress and Exposition (ECCE) - A CMOS-Based Energy Harvesting Approach for Laterally-Arrayed Multi-Bandgap Concentrated Photovoltaic Systems
摘要: This paper presents an energy harvesting approach for a concentrated photovoltaics (CPV) system based on cell-block-level integrated CMOS converters. The CPV system, built upon the Laterally-Arrayed Multi-Bandgap (LAMB) cell structure, is a potentially higher-efficiency and lower-cost alternative to traditional tandem-based systems. The cells within a sub-module block are connected for approximate voltage matching, and a CMOS-based multi-input single-output converter harvests and combines the energy while performing maximum power point tracking (MPPT) locally. First, a comparison of modeled performances achievable with traditional tandem CPV and LAMB CPV with a MISO converter is presented using day-long outdoor measured solar spectrum. The model predicts on average >19% more energy can be extracted from LAMB modules on a typical day. Then, a prototype miniaturized MISO dc-dc converter operating at 10MHz is developed in a 130nm CMOS process. For 45-160mW power levels, the prototype converter achieves >92% nominal and >95% peak efficiency in a small form factor designed to fit within available space in a LAMB PV cell block. The results demonstrate the potential of the LAMB CPV architecture for enhanced solar energy capture.
关键词: energy harvesting,maximum power point tracking,concentrated photovoltaic systems,CMOS,MISO dc-dc converter,DC-DC power converters
更新于2025-09-11 14:15:04
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A PWM based readout circuit for optical sensors with adaptive frequency control
摘要: This paper proposes a pulse-width modulation-based readout circuit for optical sensors which adopts adaptive frequency control technique to enhance input dynamic range of current sensing systems. The proposed readout circuit is designed and fabricated using a 65 nm CMOS process. The readout IC achieves 100 dB of dynamic range in current sensing system by adaptively controlling the frequency of operating clock.
关键词: photodiode,current to PWM converter,trans-impedance amplifier,pulse-width modulation,CMOS,optical sensor
更新于2025-09-11 14:15:04