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Heavily Irradiated 65-nm Readout Chip With Asynchronous Channels for Future Pixel Detectors
摘要： This paper discusses the main results relevant to the characterization of an analog front-end processor designed in view of experiments with unprecedented particle rates and radiation levels at the high-luminosity Large Hadron Collider (HL-LHC). The front-end channel presented in this paper is part of the CHIPIX65-FE0 prototype, a readout application-speci?ed integrated circuit designed in a 65-nm CMOS technology in the frame of the CERN RD53 collaboration. The prototype integrates a 64 × 64 pixel matrix, divided into two 32 × 64 submatrices, featuring squared pixels with 50-μm pitch, embodying two analog front-end architectures based on synchronous and asynchronous hit discriminators. This paper is focused on the characterization of the array with asynchronous channels, before and after exposure to ionizing doses up to 630 Mrad(SiO2) of X-rays. The analog chain takes a per-channel area close to 1000 μm2, with a power dissipation of around 5 μW. The mean value of the equivalent noise charge, not signi?cantly affected by radiation, is close to 100 electrons with no sensor connected to the front end. The threshold dispersion before irradiation is 55 electrons, for a tuned threshold of 600 electrons, with a moderate increase after irradiation. In-pixel analog-to-digital conversion, based on the time-over-threshold technique, is not appreciably in?uenced by the radiation as well. The assessed performance guarantees sub-1000 electrons stable threshold operations, which is a mandatory feature for highly ef?cient readout chips at the HL-LHC.
关键词： pixel readout,Analog front ends,electronic noise,CMOS processes,ionizing radiation effects
更新于2025-09-23 15:21:01
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Single electron transistors with e-beam evaporation of SiO <sub/>2</sub> tunnel barriers
摘要： Recent work on fabricating metal-insulator-metal (MIM) single electron transistors (SETs) using deposited dielectrics shows promise for becoming a manufacturable process due to compatibility with modern CMOS processes. This process, the “rib-SET” process [V. Joshi, A. O. Orlov, and G. L. Snider, J. Vac. Sci. Technol. B 26, 2587 (2008); G. Karbasian, A. O. Orlov, and G. L. Snider, J. Vac. Sci. Technol. B 33 (2015)], features a self-aligned island and should allow for scaling SETs below 10 nm. However, one of the biggest roadblocks in realizing a high-quality SET with this process has been dif?culties in developing high-quality, low-noise, MIM tunnel junctions. In this work, the authors report Pt-SiO2-Pt MIM SETs with tunnel barriers deposited by e-beam evaporation as an alternative to atomic layer deposition. There are some challenges in the formation of tunnel barriers via e-beam evaporation that are addressed. It is expected that platinum has a negligible native oxide; however, there is a substantial resistance in as-deposited Pt-SiO2-Pt structures that can be reduced by over 5 orders of magnitude by subjecting the ?nished devices to an anneal in a hydrogen plasma, suggesting the presence of an interfacial platinum oxide. It is shown that this treatment not only increases the conductance through the SET, but that it is necessary for forming high conductance tunnel barriers that are desired for making low-noise SETs.
关键词： single electron transistors,metal-insulator-metal,e-beam evaporation,SiO2 tunnel barriers,CMOS processes
更新于2025-09-09 09:28:46