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[IEEE 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Porto, Portugal (2018.10.10-2018.10.12)] 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Real-Time Analysis of Living Biological Cell Activity
摘要： This demo shows a computing system able to process data from electrophysiology cultures in real-time. It is the first one able to identify eventual relationship among living cells from the cell activity signals. The hardware demonstrator is able to acquire data from 64 analog signals sampled at 10kHz, but the computing architecture is flexible enough to provide various number of input electrodes depending of its configuration. Most of the parameters are user definable without reconfiguration to ensure the usability of the system for real-life biology experiment.
关键词： biological cell activity,FPGA,HLS,electrophysiology,spike detection,inter-channel correlation,real-time analysis
更新于2025-09-23 15:23:52
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[IEEE 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Porto, Portugal (2018.10.10-2018.10.12)] 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Real-Time Implementation of Contextual Image Processing Operations for 4K Video Stream in Zynq UltraScale+ MPSoC
摘要： In this paper hardware implementation of selected contextual based image pre-processing modules for a 3840×2160@60fps video stream in a Zynq UltraScale+ MPSoC is discussed. The following operations are considered: simple averaging (box filter), Gaussian filter, edge detection using the Sobel and Canny methods, median filter and morphological erosion and dilation operations. The scheme for implementing contextual based operations for a video stream in the format of 2 and 4 pixels per clock and challenges related to the pipelined implementation of processing such data are described. Also the use of logic resources and energy efficiency of modules described in the Verilog hardware description language and using the High Level Synthesis tools (Vivado HLS, SDSoC and xfOpenCV library) are compared. All designed modules support real-time processing of a 4K@60fps video stream.
关键词： FPGA,Zynq SoC,Canny,Vivado HLS,xfOpenCV,real-time processing,SDSoC,image pre-processing,Sobel,contextual based filtering
更新于2025-09-23 15:22:29