- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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Study of Power Consumption of Timepix3 Detector
摘要： The Timepix3 readout chip — the latest member of the Medipix family of hybrid pixel detectors — brought several new functionalities in comparison with the older Timepix, i.e. a high hit-rate, a time granularity of 1.5625 ns, a data-driven readout scheme (with a per pixel dead time of approximately 475 ns), and the capability of measuring Time-over-Threshold (ToT) and Time-of-Arrival (ToA) in each pixel at the same time. However, the high power consumption of the Timepix3 in the standard setting prevents its use in applications with limited power budget. Moreover, the high power consumption poses the risk of overheating the sensor so that proper cooling is crucial. The presented work investigates the effect of different settings in the analogue and a digital part of the Timepix3 detector on its power consumption. Measurements were performed with the Timepix3 chipboard. The firmware of the Katherine readout was modified so that the user can monitor the power consumptions of analogue and digital part “on-line” (directly in the control software). In standard settings, a power consumption of approximately 1.3 W was found. By changes of internal DACs, the consumption could be reduced to 650 mW. Further reduction was achieved by the change of the clock management in the digital part of the Timepix3. In result, a power consumption of 216 mA could be achieved. In these low power settings, the ToA clock was reduced to 10 MHz and thus the time binning was 100 ns. The energy resolution was not affected significantly. The pixel dead time is also negatively affected when the matrix clock is reduced. In the case of 10 MHz, the minimal per pixel dead time is 1.9 μs.
关键词： databases),Detector control systems (detector and experiment monitoring and slow-control systems,Data acquisition concepts,hardware,algorithms,architecture
更新于2025-09-23 15:23:52
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[IEEE 2018 IEEE 2nd Colombian Conference on Robotics and Automation (CCRA) - Barranquilla, Colombia (2018.11.1-2018.11.3)] 2018 IEEE 2nd Colombian Conference on Robotics and Automation (CCRA) - Modeling and Simulation of a Grid-Tied 21.0 kWp Real Solar Power Plant as Case Study, Using the VHDL-AMS Language
摘要： This paper presents the utilization of hardware description language VHDL-AMS (Very High-Speed Integrated Circuit plus Hardware Description Language that includes analog and mixed-signal extensions) for modeling and simulation a grid-tied 21.0 kWp real solar power plant, admitted as case study. The case study used in this research consists of a photovoltaic power system with the following features: 1) It has 90 panels of 255 Wp and 3 SMA On Grid inverters, 2) It operates without batteries, and 3) It has a dynamic power controller, called Circuitor (CDP-0), to guarantee zero injection into the grid. The main contribution of this work is modeling and simulation of a grid-tied real solar power plant, using the VHDL-AMS language (with the support of software SystemVision?), in order to develop a simulating tool capable to find the real electrical energy generation in a photovoltaic system, considering the monthly averaged direct normal radiation and the solar panel characteristics. This paper aims to present the first major developments for the future construction of a bigger VHDL-AMS tool that will allow the simulation of photovoltaic power systems, operating in a synergic way with hydroelectric power plants previously built, with the aim of optimize the coordinated operation between hydropower and solar energy, for periods of rain and hydrological drought.
关键词： Solar Power Plant,Hardware description languages,VHDL-AMS Language,Photovoltaic systems
更新于2025-09-23 15:23:52
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Characterisation of Timepix3 with 3D sensor
摘要： Tests were performed at the SPS facilities at CERN using a 40 GeV/c pion beam with prototype 3D-Timepix3 detectors (3D detector). A planar-Timepix3 (planar detector) was placed along the beam axis together with the 3D detectors in a telescope arrangement for comparison and reference. We demonstrate that the combination of 3D-geometry silicon sensors and Timepix3 module can reduce the effect of charge sharing and lowers the carrier drift-time, while giving the same spectroscopy performance without sacrificing the timing or any performance advantages of the Timepix3 module.
关键词： Performance of High Energy Physics Detectors,databases),Detector control systems (detector and experiment monitoring and slow-control systems,hardware,algorithms,architecture
更新于2025-09-23 15:23:52
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Development of the readout system for a time projection chamber prototype
摘要： A new GEM-TPC prototype with a laser calibration system is being designed to study the key issues of high-precision track detection whose aimed spatial resolution is better than 100 μm. Meanwhile, a readout system with scalability for the TPC is also being developed. Design of the readout system is based on the architecture of front-end ASICs and commercial ADCs for its advantages at high count rates. Given the requirement of several hundred channels, the system is composed of multiple front-end cards and DAQ boards. The DAQ boards are daisy-chained via bidirectional optical fibers, which transmit clock, trigger, data and control signals simultaneously. To achieve timing synchronization, the GigaBit Transceiver (GBT) firmware is employed to ensure fixed latency between the boards. This paper is focused on the design and setup of the DAQ system, including clock structure, trigger alignment, high-speed data acquisition, etc. The DAQ system consisting of 512 channels has been built, and tests have proved that the entire system works correctly and meets the expected requirements.
关键词： Trigger concepts and systems (hardware and software),Electronic detector readout concepts (gas, liquid),Modular electronics,Data acquisition concepts
更新于2025-09-23 15:22:29
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[IEEE 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Porto, Portugal (2018.10.10-2018.10.12)] 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Hardware-Software Implementation of a SFM Module for Navigation an Unmanned Aerial Vehicles-A Demo
摘要： In this paper the design of an embedded vision system for structure from motion (SFM) computation is presented. The solution allows for scene depth reconstruction based on two consecutive video frames registered by a moving camera. The module is developed for a Xilinx Zynq SoC (System on Chip) device and is divided into a hardware and software part. The programmable logic (PL) is used mainly for detect and match features. Fundamental matrix estimation and triangulation are executed in the processing system (PS – ARM based). The module is dedicated to navigation of unmanned aerial vehicles (UAV) – autonomous flight and landing. The system is adapted to process a 1280x720 pixel video stream @60 frames per second in real-time.
关键词： FPGA,Zynq SoC,structure from motion,real-time video processing,hardware-software systems
更新于2025-09-23 15:22:29
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Fast sampling from Wiener posteriors for image data with dataflow engines
摘要： We use Dataflow Engines (DFE) to construct an efficient Wiener filter of noisy and incomplete image data, and to quickly draw probabilistic samples of the compatible true underlying images from the Wiener posterior. Dataflow computing is a powerful approach using reconfigurable hardware, which can be deeply pipelined and is intrinsically parallel. The unique Wiener-filtered image is the minimum-variance linear estimate of the true image (if the signal and noise covariances are known) and the most probable true image (if the signal and noise are Gaussian distributed). However, many images are compatible with the data with different probabilities, given by the analytic posterior probability distribution referred to as the Wiener posterior. The DFE code also draws large numbers of samples of true images from this posterior, which allows for further statistical analysis. Naive computation of the Wiener-filtered image is impractical for large datasets, as it scales as n3, where n is the number of pixels. We use a messenger field algorithm, which is well suited to a DFE implementation, to draw samples from the Wiener posterior, that is, with the correct probability we draw samples of noiseless images that are compatible with the observed noisy image. The Wiener-filtered image can be obtained by a trivial modification of the algorithm. We demonstrate a lower bound on the speed-up, from drawing 105 samples of a 1282 image, of 11.3 ± 0.8 with 8 DFEs in a 1U MPC-X box when compared with a 1U server presenting 32 CPU threads. We also discuss a potential application in astronomy, to provide better dark matter maps and improved determination of the parameters of the Universe.
关键词： Reconfigurable hardware,MCMC,Data analysis,Wiener filter,Bayesian statistics,Dataflow engines
更新于2025-09-23 15:22:29
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[IEEE IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society - D.C., DC, USA (2018.10.21-2018.10.23)] IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society - Controller-Hardware-in-the-Loop Testbed for Fast-Switching SiC-Based 50-kW PV Inverter
摘要： The recent advent of wide bandgap power semiconductor devices will lay the path for future power converters. These devices provide the advantage of high switching speed and lower losses. The high cost and high switching speeds of these devices provide a challenge in the development and validation of the fast-switching inverter controls with accuracy comparable to that of a hardware setup. In this paper, a field programmable gate array (FPGA) real-time simulator-based controller-hardware-in-the-loop (CHIL) testbed is used to verify the low-level and advanced inverter controls for fast-switching wide bandgap-based photovoltaic string inverter. The paper also includes development of the CHIL testbed, which is run at a time step of 500 ns in order to implement 20-kHz switching frequency. The developed CHIL testbed is validated through experimental results from a three-phase, 50-kW, 480-VLLrms SiC device-based inverter.
关键词： controller hardware-in-the-loop,high switching frequency,SiC devices,power electronics converters,advanced grid-support functions
更新于2025-09-23 15:22:29
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[IEEE 2018 IEEE International Conference on Automation/XXIII Congress of the Chilean Association of Automatic Control (ICA-ACCA) - Concepcion, Chile (2018.10.17-2018.10.19)] 2018 IEEE International Conference on Automation/XXIII Congress of the Chilean Association of Automatic Control (ICA-ACCA) - Mobile LiDAR Scanner for the Generation of 3D Georeferenced Point Clouds
摘要： Mobile laser scanning systems are a modern tool used by leading companies in surveying. These systems are capable of making a three-dimensional reconstruction of the environment by capturing thousands of aligned points. This article describes a hardware and software-based solution for a 3D LiDAR scanner capable of generating a georeferenced point cloud. This solution uses an integrated microcomputer-based hardware architecture, integration of navigation components and data logging. In addition, the effect caused by the measurement errors of the inertial sensors is displayed. To minimize these undesired effects, the use of high-precision navigation system is necessary. For the estimation of the position and orientation of the data captured by the LiDAR sensor, a non-linear interpolation is used for the oversampling of navigation data. Likewise, the scientific problem of direct georeferencing is modeled with a mathematical approach to conventional robotic structure. The product developed meets the technical requirements for most applications in topographic surveys and structural modeling. The system is portable on multiple platforms such as land vehicles and unmanned aerial vehicles.
关键词： point cloud,LiDAR,georeferencing,INS,MLS,hardware
更新于2025-09-23 15:22:29
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Robust Model Predictive Control (MPC) for large-scale PV plant based on paralleled three-phase inverters
摘要： In this contribution a robust Model Predictive Control (MPC) is proposed to enhance the power quality of a large-scale PV plant connected to the grid through Paralleled Voltage Source Inverters (PVSIs) with common AC and DC buses. Paralleling inverters allow handling high-power export and offer advantages in terms of redundancy which ensure the system reliability. However, due to the physical differences and parameter disparities between the inverters, zero sequence circulating currents will flow through it, which will disturb the performance of the system. Hence, the control goal is to regulate the currents injected into the grid, suppress the zero-sequence circulating current (ZSCC). Consequently, this study proposes an MPC algorithm that is based on optimization approach which allows minimizing circulating currents. In order to show its effectiveness and performance of the proposed control, a comparison with linear PI controller is included. In addition, design control and tuning procedure are detailed. Simulation results show the performance of the proposed controller in ensuring power quality, and suppressing circulating currents. To verify the real-time feasibility of the proposed control scheme, Hardware-In-the-Loop (HIL) setup is carried out with means of Opal-RT and dSPACE rapid prototyping systems.
关键词： Hardware-in-the-loop,Model predictive control,PV power plant,Grid-connected inverter,Circulating current,Parallel operation
更新于2025-09-23 15:21:01
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LOCx2-130, a low-power, low-latency, 2 × 4.8-Gbps serializer ASIC for detector front-end readout
摘要： In this paper, we present the design and test results of LOCx2-130, a low-power, low-latency, dual-channel transmitter ASIC for detector front-end readout. LOCx2-130 has two channels of encoders and serializers, and each channel operates at 4.8 Gbps. LOCx2-130 can interface with three types of ADCs, an ASIC ADC and two COTS ADCs. LOCx2-130 is fabricated in a commercial 130-nm CMOS technology and is packaged in a 100-pin QFN package. LOCx2-130 consumes 440 mW and achieves a latency of less than 40.7 ns.
关键词： Trigger concepts and systems (hardware and software),Digital electronic circuits,Front-end electronics for detector readout
更新于2025-09-23 15:21:01