- 标题
- 摘要
- 关键词
- 实验方案
- 产品
-
[IEEE 2018 IEEE CPMT Symposium Japan (ICSJ) - Kyoto, Japan (2018.11.19-2018.11.21)] 2018 IEEE CPMT Symposium Japan (ICSJ) - 400G Multi-Mode and Single-Mode Optical Transmitter Realized by Hybrid-Integrated Silicon Interposer for Data Center Application
摘要： We experimentally demonstrated both 400G multi-mode (MM) and single-mode (SM) optical engines based on Silicon interposer to hybrid integrate laser dice, optics, and fiber arrays. The interposer realized by Silicon bulk micro-machining makes the engine very compact and easily assembled by the built-in Silicon precision. Clear optical eyes with TDECQ of 1.7dB and of 2.7 dB are obtained for 50Gb/s VCSEL in MM optical engine and 100Gb/s EML in SM one, respectively.
关键词： Optical Engine,Hybrid-Integration,VCSEL,Optical Sub-Assembly (OSA),and EML Laser,Silicon Interposer,Silicon Photonics
更新于2025-09-23 15:22:29
-
Fabrication and characterization of a low-cost interposer with an intact insulation layer and ultra-low TSV leakage current
摘要： The application of a Si interposer is hindered by its complicated manufacturing process, high cost and some reliability challenges such as through silicon via (TSV) leakage. In this paper, a fabrication approach using a Si interposer is proposed, which can simplify the manufacturing process significantly and reduce the cost by more than 40%. Benefiting from the simplified process, the TSV insulation layer stays intact during the whole manufacturing process, an ultra-low TSV leakage current can be obtained. To evaluate the performance and reliability of the interposer, test samples consisting of 136 TSVs are designed and fabricated. A series of tests are carried out to verify the electrical insulating performance and reliability of the interposer. Under the bias voltage of 5 V, the TSV leakage current is 2.05 × 10?14 A, which is much lower than the usual value in the range of 10?12 –10?9 A. The yield of daisy chains exceeds 91.66% and that of individual TSVs is more than 99.91%. All the interposer samples have successfully passed the thermal cycle test, and the resistance variation of each individual pathway is within 5% after 200 cycles.
关键词： interposer,insulation layer,TSV leakage current,3D-IC integration
更新于2025-09-23 15:21:21
-
Benchmarking Digital Die-to-Die Channels in 2.5-D and 3-D Heterogeneous Integration Platforms
摘要： In this paper, compact circuit models and HSPICE simulations are used to benchmark die-to-die communication channels in 2.5-D and 3-D heterogeneous integration platforms. The delay, energy-per-bit, and bandwidth-density of the considered integration platforms are simulated and benchmarked. Compared to other 2.5-D integrated systems with a 1-mm interconnect length, heterogeneous interconnect stitching technology (HIST)-based 2.5-D integration shows a maximum latency and energy reduction of 6.2% and 15.1%, respectively. 3-D ICs show further performance enhancement compared to 2.5-D integration; the link latency and energy are approximately 19.4% and 48.0% smaller than those of HIST (1-mm wire) for through-silicon via (TSV)-based 3-D integration (75-μm TSV height). Next, the impacts of the physical I/O interconnect dimensions and device process technology scaling are evaluated and we observe that advanced process technologies must be integrated with smaller physical I/O dimensions and shorter wire lengths to attain full advantages of scaling. Finally, we consider the thermal impact of dense heterogeneous integration and investigate the thermal and electrical signaling tradeoffs in 2.5-D and 3-D integration.
关键词： Die-to-die interconnect,interposer and bridge-chip 2.5-D ICs,signaling
更新于2025-09-23 15:21:01
-
Femtosecond laser additive and subtractive micro-processing: enabling a high-channel-density silica interposer for multicore fibre to silicon-photonic packaging
摘要： Great strides have been made over the past decade to establish femtosecond lasers in advanced manufacturing systems for enabling new forms of non-contact processing of transparent materials. Research advances have shown that a myriad of additive and subtractive techniques is now possible for flexible 2D and 3D structuring of such materials with micro- and nano-scale precision. In this paper, these techniques have been refined and scaled up to demonstrate the potential for 3D writing of high-density optical packaging components, specifically addressing the major bottleneck for efficiently connecting optical fibres to silicon photonic (SiP) processors for use in telecom and data centres. An 84-channel fused silica interposer was introduced for high-density edge coupling of multicore fibres (MCFs) to a SiP chip. Femtosecond laser irradiation followed by chemical etching (FLICE) was further harnessed to open alignment sockets, permitting rapid assembly with precise locking of MCF positions for efficient coupling to laser written optical waveguides in the interposer. A 3D waveguide fanout design provided an attractive balancing of low losses, mode-matching, high channel density, compact footprint, and low crosstalk. The 3D additive and subtractive processes thus demonstrated the potential for higher scale integration and rapid photonic assembly and packaging of micro-optic components for telecom interconnects, with possible broader applications in integrated biophotonic chips or micro-displays.
关键词： multicore fibre,waveguide fanout,silicon photonics interposer,space-division multiplexing,fibre socket,femtosecond laser micro-processing,photonic packaging
更新于2025-09-23 15:19:57
-
[IEEE 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) - Xi'an, China (2019.6.12-2019.6.14)] 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) - Polarization measurement method of semiconductor laser
摘要： A high-density low-power parallel I/O for die-to-die communication is presented. The proposed interface includes a low-power transceiver and a high-density low-cost silicon interposer. The link architecture exploits single-sided and capacitive termination, passive equalization in the transmitter, and CMOS logic-style circuits to reduce the power consumption. To achieve a high bump/wire efficiency, single-ended signaling is used. A 4-layer Aluminum silicon interposer is fabricated providing 2.5 mm and 3.5 mm links between prototype transceivers. The transceiver prototype includes 3 transmitters and 3 receivers fabricated in 28 nm STM FD-SOI CMOS technology. The parallel interface operates at 20 Gb/s/wire and 18 Gb/s/wire data rates over the 2.5 mm and 3.5 mm channels with 5.9 and 7.7 dB of loss relative to DC (10.7 and 13.5 dB total loss) at while consuming 0.30 and 0.32 pJ/bit excluding clocking circuits, respectively.
关键词： Chip-to-chip communication,high-speed I/O,silicon Interposer,die-to-die communication,termination,single-ended signaling,passive equalizer,low-power transceivers
更新于2025-09-19 17:13:59
-
[IEEE 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Las Vegas, NV, USA (2019.5.28-2019.5.31)] 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Vertical Laser Assisted Bonding for Advanced "3.5D" Chip Packaging
摘要： In this work the processes of laser assisted bonding (LAB) is compared to thermal compression bonding (TCB). Their respective advantages and disadvantages regarding the assembly of flip chip stacks are compared. It is found, that the LAB allows for faster processing, negligible compression force and creates less internal stress in the chip stack. The concept of “3.5D” stacking is introduced. This new concept allows for the vertical bonding of chips/semiconductors to the sides of a chip stack. The vertically bonded parts can be used to contact the layers, which eliminates the individual necessity for through silicon vias (TSVs).
关键词： 3D-packaging,Silicon interposer,Thermal compression bonding (TCB),Inter metallic phase (IMC-layer),Laser assisted bonding (LAB),System on Package (SOP),Laser beam modulation,vertical Flip Chip bonding
更新于2025-09-16 10:30:52
-
[IEEE 2019 International Conference on Electronics Packaging (ICEP) - Niigata, Japan (2019.4.17-2019.4.20)] 2019 International Conference on Electronics Packaging (ICEP) - High-speed High-density Cost-effective Cu-filled Through-Glass-Via Channel for Heterogeneous Chip Integration
摘要： A topside Cu-filled through-glass via ("Cu bridge") is presented as a novel transmission channel. The simulated signal transmission loss of the Cu bridge was as low as 0.04 dB at a signal frequency of 18 GHz, corresponding to the PCI Express 5.0 bus standard. Its signal transmission loss was less than 0.13 % in a typical long-reach SerDes channel with a loss of 30 dB. The minimum pitch of the Cu bridge was as narrow as 100 μm, which meets the requirements for increased signal I/O. The simple few-step fabrication of the Cu bridge effectively reduces the cost of manufacturing glass interposers. This is a great advantage compared to silicon interposers, which require a complicated process to fabricate Cu through-silicon vias. A glass substrate semi-additive and embedded with Cu bridges supports damascene-based redistribution layers, which increases the number of potential packaging configurations. This Cu bridge is thus a promising approach to next-generation heterogeneous integration based on 2.nD interposers.
关键词： Interposer,TSV,2.nD,TGV,Redistribution layer,Heterogeneous integration,2.5D,Semi-additive process,2.1D,Damascene,RDL,Through-glass via,Through-silicon via
更新于2025-09-16 10:30:52
-
Micromachined Waveguide Interposer for the Characterization of Multi-port Sub-THz Devices
摘要： This paper reports for the first time on a micromachined interposer platform for characterizing highly miniaturized multi-port sub-THz waveguide components. The reduced size of such devices does often not allow to connect them to conventional waveguide flanges. We demonstrate the micromachined interposer concept by characterizing a miniaturized, three-port, 220–330-GHz turnstile orthomode transducer. The interposer contains low-loss micromachined waveguides for routing the ports of the device under test to standard waveguide flanges and integrated micromachined matched loads for terminating the unused ports. In addition to the interposer, the measurement setup consists of a micromachined square-to-rectangular waveguide transition. These two devices enable the characterization of such a complex microwave component in four different configurations with a standard two-port measurement setup. In addition, the design of the interposer allows for independent characterization of its sub-components and, thus, for accurate de-embedding from the measured data, as demonstrated in this paper. The measurement setup can be custom-designed for each silicon micromachined device under test and co-fabricated in the same wafer due to the batch nature of this process. The solution presented here avoids the need of CNC-milled test-fixtures or waveguide pieces that deteriorate the performance of the device under test and reduce the measurement accuracy.
关键词： Test-fixture,Orthomode transducer,Terahertz,Multi-port,Measurement,Interposer,Silicon micromachining,Waveguide,DRIE
更新于2025-09-16 10:30:52
-
Innovative Sub-5 Micron Microvias by Picosecond UV Laser for Post-Moore Packaging Interconnects
摘要： This paper presents for the first time microvias scaled down to sub-5 μm in diameter fabricated using picosecond UV laser ablation in a non-photoimageable dielectric film. The motivation of this work is to address post-Moore and More-than- Moore packaging interconnect needs. Microvias play a critical role in package interconnections in IO density and the IC bump pitch for 2.5D interposers and fan-out packages. UV laser ablation has been the key technology for fabricating small microvias in high density interconnect (HDI) packaging for more than two decades. The state-of-the-art microvia fabricated by UV laser ablation is still at 20 μm in diameter and 50 μm in pitch. This study explores the feasibility of fabricating microvias of 5 μm or less in diameter with a commercially available picosecond UV laser system. The experimental results show that microvias of 5 μm or less in diameter in a 5 μm thick Ajinomoto buildup dielectric film (ABF) are achieved. This paper also addresses fundamentals of picosecond pulsed laser ablation on polymer dielectric materials, and process optimization to generate sub-5 micron microvias. The via pitch of 8 μm to 12 μm is demonstrated. UV laser ablation also addresses the issue of limited availability of photosensitive dielectric materials for photolithography based microvia fabrication.
关键词： RDL,2.5D interposer,fan-out package,Microvia,interconnect,picosecond UV laser
更新于2025-09-12 10:27:22
-
[IEEE 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Las Vegas, NV, USA (2019.5.28-2019.5.31)] 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Fully-Filled, Highly-Reliable Fine-Pitch Interposers with TSV Aspect Ratio >10 for Future 3D-LSI/IC Packaging
摘要： Si interposer with 10 μm-width, 100 μm-deep through-silicon via (TSV) has been fabricated using electroless (EL) Ni as barrier and seed layers, and characterized for their electrical resistance. The chemistry of electroless-Ni plating bath was meticulously adjusted for the conformal formation of Ni along the TSV side wall. From the resistance value of 36 mΩ per TSV obtained from the Kelvin measurement of these Cu-TSV chain showed that the electroless Ni layer well acts as a good seed layer for completely filling the high aspect ratio TSVs by Cu-electroplating.
关键词： Barrier/Seed layer,Si interposer,Cu-TSV,Electroless Ni,Cu-diffusion
更新于2025-09-12 10:27:22