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Poly‐GeSn Junctionless Thin‐Film Transistors on Insulators Fabricated at Low Temperatures via Pulsed Laser Annealing
摘要： High-performance polycrystalline GeSn (poly-GeSn) junctionless thin-film transistors (JL-TFTs) are proposed and fabricated at low process temperatures. Poly-GeSn thin films with a Sn fraction of 4.8% are prepared using cosputtering and pulsed laser annealing (PLA) techniques. The ultra-rapid nonequilibrium thermodynamic process with 25 ns PLA renders a good crystal GeSn thin film at a low temperature. The ION/IOFF ratio increases by three orders of magnitude with GeSn channel thickness varying from 60 to 10 nm, suggesting that switch-off current is dominated by depletion width. A superior effective mobility of 54 cm2 V-1 s-1 is achieved for the JL-TFT with a 10 nm-thick GeSn film as a consequence of gate/channel interface passivation by oxygen plasma.
关键词： pulsed laser annealing,junctionless thin-film transistors,GeSn
更新于2025-09-11 14:15:04
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A new ultra-scaled graphene nanoribbon junctionless tunneling field-effect transistor: proposal, quantum simulation, and analysis
摘要： In this paper, a new ultrascaled junctionless graphene nanoribbon tunnel field-effect transistor (JL GNRTFET) is proposed through a computational study. The quantum simulation approach is based on the resolution of the Schr?dinger equation using the mode space non-equilibrium Green’s function formalism coupled self-consistently with a Poisson equation in the ballistic limit. The proposed nanodevice is endowed with ungated region between the auxiliary and control gates as well as with a laterally graded channel doping in order to improve the switching performance of the ultrascaled junctionless GNRTFET. The performance assessment has included the IDS–VGS transfer characteristics, subthreshold swing, current ratio, intrinsic delay, and power-delay product. It has been found that the proposed ultrascaled junctionless GNR tunneling FET can provide improved switching performance than its conventional counterpart. The proposed strategy can be applied to improve similar ultrascaled junctionless tunneling field-effect transistors for the future digital electronics, where the high-performance and the aggressive downscaling should be in agreement.
关键词： Junctionless,Graphene nanoribbon (GNR),Tunneling field-effect transistor (TFET),Switching,Quantum simulation,Tunneling
更新于2025-09-11 14:15:04
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[Lecture Notes in Electrical Engineering] Advances in Signal Processing and Communication Volume 526 (Select Proceedings of ICSC 2018) || Mole Fraction Dependency Electrical Performances of Extremely Thin SiGe on Insulator Junctionless Channel Transistor (SG-OI JLCT)
摘要： In this paper, the single-gate junctionless (JL) MOSFET with extremely thin silicon germanium (SiGe) device layer on insulator (ETSG-OI) is explored to identify the short channel effects (SCEs) and electrical behavior of the device. The device incorporates various engineering schemes (channel and spacer engineering scheme) with JL topology on SOI platform. The in?uence of the SiGe device layer with mole fraction (x) variation (x (cid:2) 0.25, 0.5, 0.75) is investigated to understand the bandgap differences of the device. Depending on the change in Ge mole fraction, the energy potential, electric ?eld, and drain induced barrier lowering (DIBL) performances are analyzed. From the simulation results at x (cid:2) 0.25, the ETSG-OI JLCT shows reasonable improvement in ON current (I ON) and DIBL at both linear and saturation drain voltages. For different values of x, the energy bandgap tends to vary from 0.6?1.1 eV. It is observed that at x (cid:2) 0.25 the bandgap is 0.8 eV which is almost near to the bandgap of Si material due to the 25% existence of Ge material.
关键词： Electrical performances,Silicon germanium,Drain induced barrier lowering,I ON-I OFF,Junctionless MOSFET
更新于2025-09-10 09:29:36
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Self-organized Ge nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet n-FETs featuring high ON-OFF drain current ratio
摘要： We reported experimental fabrication and characterization of Si0.15Ge0.85 n-MOSFETs comprising a gate-stacking of Ge-nanospherical gate/SiO2/Si0.15Ge0.85-nanosheet on SOI (100) substrate in a self-organization approach. This unique gate-stacking heterostructure is simultaneously produced in a single oxidation step as a consequence of an exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials at 900oC. Process-controlled tunability of nanospherical gate of 60?100nm in diameter, gate oxide thickness of 3nm, and Si0.15Ge0.85 nanosheet with compressive strain of -2.5% was achieved. Superior gate modulation is evidenced by subthreshold slope of 150mV/dec and ION/IOFF > 5×108 (IOFF < 10-6 μA/μm and ION > 500 μA/μm) measured at VG = +1V, VD = +1V, and T = 80K for our device with channel length of 75nm.
关键词： self organization,Ge-gate,SiGe nanosheet,junctionless FET
更新于2025-09-10 09:29:36