- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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[IEEE 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) - Tainan, Taiwan (2018.11.5-2018.11.7)] 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) - A CMOS 76-81 GHz 2TX 3RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator
摘要： A fully integrated 76-81 GHz frequency-modulated continuous-wave (FMCW) radar transceiver (TRX) in 65nm CMOS is presented. Two transmitters (TXs) and three receivers (RXs) are integrated for MIMO processing. A 38.5 GHz mixed-mode PLL with reconfigurable loop bandwidth and frequency doubling scheme are employed to generate the reconfigurable FMCW chirp waveforms. Passive voltage-mode down-conversion is utilized to improve the RX linearity against TX leakage. A bottom-switching PA is proposed to realize the Bi-Phase modulation, and the magnetically-coupled resonator technique is used to effectively expand the link bandwidth. Measurement results show that the FMCW TRX could generate reconfigurable chirps with the bandwidth from 250 MHz to 4 GHz and the period from 600 us to 10 ms. The root-mean-square (RMS) frequency error is less than 251 kHz. The TX maximum output power is 13.4 dBm and is adjustable within 3 dB by reconfiguring its LDO output voltage. The RX achieves 15.3 dB noise figure and -8.5 dBm RF input-referred PldB. Real-time experiments are carried out using the proposed TRX chip, in which the measured average distance error is 10 cm. The overall power consumption is 921mW with 2-TXs and 3-RXs powered on.
关键词： transceiver,PLL,CMOS,mm-wave,Radar,frequency-modulated continuous-wave (FMCW)
更新于2025-09-23 15:23:52
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[IEEE 2018 International Conference on Radar (RADAR) - Brisbane, Australia (2018.8.27-2018.8.31)] 2018 International Conference on Radar (RADAR) - Improved Tx-to-Rx Isolation of Radar Transceivers Using Integrated Full Duplexer with PLL
摘要： The isolation between transmitter and receiver for the radars is ultimately important since the transmitting radar signals can be penetrated the receiver directly in case a bad isolation is formed. This paper describes the isolation between the transceiver and the design of an integrated full duplexer using the phase locked loop (PLL). Although the antenna impedance varies arbitrarily, the PLL tracks the impedance variation in real time, leading to improvement of isolation between the transmitter and the receiver of radars. The full duplexer reduces the transmitter leakage up to 45 dB using the balance network along with the PLL in measurement.
关键词： Transceiver,Impedance tracking,PLL,Balanced network,CMOS process,Integrated Full Duplexer
更新于2025-09-23 15:22:29
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Optimization Methods for Evaluating PV Hosting Capacity of Distribution Circuits
摘要： We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.
关键词： Bluetooth Low-Energy,low-voltage oscillator,class-E/F2 power amplifier,All-digital PLL,low-power switching current-source transmitter,Internet of Things (IoT)
更新于2025-09-23 15:21:01
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[IEEE 2019 IEEE 3rd Conference on Energy Internet and Energy System Integration (EI2) - Changsha, China (2019.11.8-2019.11.10)] 2019 IEEE 3rd Conference on Energy Internet and Energy System Integration (EI2) - Harmonic Current Detection and Reactive Power Compensation Method for Photovoltaic System Based on FBD Method
摘要： In order to improve the equipment utilization of distributed photovoltaic power generation system, the harmonic and reactive currents generated by grid-connected photovoltaic can be accurately detected and compensated. A phase-locked loop based on second-order generalized integrator (SOGI-PLL) is introduced into the traditional FBD current detection method to separate the positive and negative sequence components of unbalanced voltage and detect the phase and frequency of reference voltage more accurately. The simulation results show that the algorithm can reduce the computational complexity and increase the detection accuracy and steady-state performance.
关键词： harmonic current detection,reactive power compensation,improved FBD method,grid-connected PV system,SOGI-PLL
更新于2025-09-23 15:21:01
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Design of c-band telecontrol transmitter local oscillator for UAV data link
摘要： A C-band local oscillator of an Unmanned Aerial Vehicle (UAV) data link radio frequency (RF) transmitter unit with high-stability, high-precision and lightweight was designed in this paper. Based on the highly integrated broadband phase-locked loop (PLL) chip HMC834LP6GE, the system performed fractional-N control by internal modules programming to achieve low phase noise and small frequency resolution. The simulation and testing methods were combined to optimize and select the loop filter parameters to ensure the high precision and stability of the frequency synthesis output. The theoretical analysis and engineering prototype measurement results showed that the local oscillator had stable output frequency, accurate frequency step, high spurious suppression and low phase noise, and met the design requirements. The proposed design idea and research method have theoretical guiding significance for engineering practice.
关键词： local oscillator,UAV,HMC834LP6GE,C-band,data link,PLL
更新于2025-09-23 15:21:01
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Autonomous Path Planning by Unmanned Aerial Vehicle (UAV) for Precise Monitoring of Large-Scale PV plants
摘要： This paper presents a 3.6 GHz low-noise fractional-N digital phase-locked loop (PLL) that achieves low in-band phase noise. Phase detection is carried out by a proposed 10-bit, 0.8 ps resolution time-to-digital converter (TDC) using a charge pump and a successive-approximation-register analog-to-digital converter (SAR-ADC) with low power and small area. The latency of the TDC is addressed by the designed building blocks. The fractional spurs are reduced by dual-loop least-mean-square (LMS) calibration. A (cid:2)(cid:3)-less and MOS varactor-less LC digitally-controlled oscillator (DCO) is proposed whose frequency resolution is enhanced to 7 kHz (or a unit variable capacitance of 2.6 aF) using a bridging capacitor technique. A prototype chip is fabricated using a 65 nm CMOS process, occupying an active area of 0.38 mm2 and consuming a power of 9.7 mW at a reference frequency of 50 MHz. The measured in-band phase noise is 107.8 dBc/Hz to 110.0 dBc/Hz with a loop bandwidth of 1 to 5 MHz.
关键词： digitally controlled oscillator (DCO),least-mean-square (LMS),digital phase-locked-loop (PLL),time-to-digital converter (TDC),successive-approximation-register analog-to-digital converter (SAR-ADC),frequency synthesizer,CMOS,sub-picosecond resolution
更新于2025-09-23 15:19:57
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[IEEE 2018 International Conference on Smart Grid and Clean Energy Technologies (ICSGCE) - Sg. Long, Cheras, Kajang, Malaysia (2018.5.29-2018.6.1)] 2018 International Conference on Smart Grid and Clean Energy Technologies (ICSGCE) - A Novel Five-Level Inverter Topology with Reactive Power Control for Grid-Connected PV System
摘要： These days multilevel inverters are more popular for grid-connected photovoltaic (PV) systems due to their low cost and high efficiency, as they effectively reduce total harmonic distortion (THD) and electromagnetic interference which results leakage current. Traditional multi-level inverters can only inject real power that cannot provide quality output power. A new international standard VDE-AR-N4105 states that for a grid tied inverter of power rating below 3.68kVA, a power factor (PF) of 0.95 leading to 0.95 lagging should be achieved. So, in this paper the proposed five-level inverter topology for grid-tie PV is controlled using a reactive power control method that ensures higher efficiency while enhancing the stability of the system. The proposed closed loop reactive power control technique additionally provides the ability to inject reactive power into the system. In this proposed topology the reactive power flow standard of operation is explained in details in relation to the proposed multi-level inverter topology. To validate the accuracy of the theoretical analysis, the control technique was applied to the existing multi-level inverter topology and then has been simulated in MATLAB/Simulink software. Comparisons were done on the basis of using and not using PLL for the existing multilevel topology and it is found that, synchronization is achieved with current and voltage if PLL is used, as a result PF is maintained close to unity whereas without PLL the PF decreases. Moreover the five-level output provides a much better output and better PF then other existing topologies.
关键词： phase-locked loop (PLL),multi-level inverters,solar PV,reactive power control
更新于2025-09-23 15:19:57
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[IEEE 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Munich, Germany (2019.6.23-2019.6.27)] 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Thermally-Induced Nonlinear Spatial Shaping of Infrared Femtosecond Pulses in Nematic Liquid Crystals
摘要： This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.
关键词： standard cell,digital varactor,small area,low power,gated injection,injection-locking,dual loop,PLL,synthesizable,logic synthesis,edge injection,low jitter,PVT,AD-PLL,DAC,CMOS
更新于2025-09-19 17:13:59
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Design guidelines for edge-coupled waveguide unitravelling carrier photodiodes with improved bandwidth
摘要： This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.
关键词： standard cell,digital varactor,small area,low power,gated injection,injection-locking,dual loop,PLL,synthesizable,logic synthesis,edge injection,low jitter,PVT,AD-PLL,DAC,CMOS
更新于2025-09-19 17:13:59
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[IEEE 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Rome, Italy (2019.6.17-2019.6.20)] 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Technological Features of Graphene-based RF NEMS Capacitive Switches on a Semi-insulating Substrate
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： sub-sampling,analog-to-digital converter (ADC),voltage-domain,All-digital phase-locked loop (AD-PLL),frequency synthesizer,CMOS,low-power
更新于2025-09-19 17:13:59