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[IEEE 2018 IEEE CPMT Symposium Japan (ICSJ) - Kyoto, Japan (2018.11.19-2018.11.21)] 2018 IEEE CPMT Symposium Japan (ICSJ) - 400G Multi-Mode and Single-Mode Optical Transmitter Realized by Hybrid-Integrated Silicon Interposer for Data Center Application
摘要： We experimentally demonstrated both 400G multi-mode (MM) and single-mode (SM) optical engines based on Silicon interposer to hybrid integrate laser dice, optics, and fiber arrays. The interposer realized by Silicon bulk micro-machining makes the engine very compact and easily assembled by the built-in Silicon precision. Clear optical eyes with TDECQ of 1.7dB and of 2.7 dB are obtained for 50Gb/s VCSEL in MM optical engine and 100Gb/s EML in SM one, respectively.
关键词： Optical Engine,Hybrid-Integration,VCSEL,Optical Sub-Assembly (OSA),and EML Laser,Silicon Interposer,Silicon Photonics
更新于2025-09-23 15:22:29
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[IEEE 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) - Xi'an, China (2019.6.12-2019.6.14)] 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) - Polarization measurement method of semiconductor laser
摘要： A high-density low-power parallel I/O for die-to-die communication is presented. The proposed interface includes a low-power transceiver and a high-density low-cost silicon interposer. The link architecture exploits single-sided and capacitive termination, passive equalization in the transmitter, and CMOS logic-style circuits to reduce the power consumption. To achieve a high bump/wire efficiency, single-ended signaling is used. A 4-layer Aluminum silicon interposer is fabricated providing 2.5 mm and 3.5 mm links between prototype transceivers. The transceiver prototype includes 3 transmitters and 3 receivers fabricated in 28 nm STM FD-SOI CMOS technology. The parallel interface operates at 20 Gb/s/wire and 18 Gb/s/wire data rates over the 2.5 mm and 3.5 mm channels with 5.9 and 7.7 dB of loss relative to DC (10.7 and 13.5 dB total loss) at while consuming 0.30 and 0.32 pJ/bit excluding clocking circuits, respectively.
关键词： Chip-to-chip communication,high-speed I/O,silicon Interposer,die-to-die communication,termination,single-ended signaling,passive equalizer,low-power transceivers
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Las Vegas, NV, USA (2019.5.28-2019.5.31)] 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Vertical Laser Assisted Bonding for Advanced "3.5D" Chip Packaging
摘要： In this work the processes of laser assisted bonding (LAB) is compared to thermal compression bonding (TCB). Their respective advantages and disadvantages regarding the assembly of flip chip stacks are compared. It is found, that the LAB allows for faster processing, negligible compression force and creates less internal stress in the chip stack. The concept of “3.5D” stacking is introduced. This new concept allows for the vertical bonding of chips/semiconductors to the sides of a chip stack. The vertically bonded parts can be used to contact the layers, which eliminates the individual necessity for through silicon vias (TSVs).
关键词： 3D-packaging,Silicon interposer,Thermal compression bonding (TCB),Inter metallic phase (IMC-layer),Laser assisted bonding (LAB),System on Package (SOP),Laser beam modulation,vertical Flip Chip bonding
更新于2025-09-16 10:30:52