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[IEEE 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Porto, Portugal (2018.10.10-2018.10.12)] 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Real-Time Implementation of Contextual Image Processing Operations for 4K Video Stream in Zynq UltraScale+ MPSoC
摘要： In this paper hardware implementation of selected contextual based image pre-processing modules for a 3840×2160@60fps video stream in a Zynq UltraScale+ MPSoC is discussed. The following operations are considered: simple averaging (box filter), Gaussian filter, edge detection using the Sobel and Canny methods, median filter and morphological erosion and dilation operations. The scheme for implementing contextual based operations for a video stream in the format of 2 and 4 pixels per clock and challenges related to the pipelined implementation of processing such data are described. Also the use of logic resources and energy efficiency of modules described in the Verilog hardware description language and using the High Level Synthesis tools (Vivado HLS, SDSoC and xfOpenCV library) are compared. All designed modules support real-time processing of a 4K@60fps video stream.
关键词： FPGA,Zynq SoC,Canny,Vivado HLS,xfOpenCV,real-time processing,SDSoC,image pre-processing,Sobel,contextual based filtering
更新于2025-09-23 15:22:29
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Femtosecond Laser Microprinting of a Polymer Optical Fiber Interferometer for High-Sensitivity Temperature Measurement
摘要： The BRAM block is a configurable memory module that attaches to a variety of BRAM interface controller. BRAM serves as a relatively large memory structure (i.e. larger than distributed RAMs or a bunch of D-flip-flop grouped together, but much smaller than off chip memory resources). In addition, multiple blocks can be cascaded to create still larger memory. The failure configuration type of BRAM in read operation was screened out by automatic test equipment (ATE). The failure pattern was created in Vivado which integrated logic analyzer (ILA) was inserted to monitor the failure BRAM data and compared against good BRAM data. The successful fault isolation of BRAM failure was mainly relied on pattern analysis as well as BRAM configuration.
关键词： Logic analyser,FPGA,Vivado,Pattern,Block RAM
更新于2025-09-11 14:15:04