- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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Improved Charge Pump Design and $Ex\ Vivo$ Experimental Validation of CMOS 256-Pixel Photovoltaic-Powered Subretinal Prosthetic Chip
摘要： An improved design of a 256-pixel photovoltaic-powered implantable chip for subretinal prostheses is presented. In the proposed subretinal chip, a high-efficiency fully-integrated 4× charge pump is designed and integrated with on-chip photovoltaic (PV) cells and a 256-pixel array with active pixel sensors (APS) for image light sensing, biphasic constant current stimulators, and electrodes. Thus the PV voltage generated by infrared (IR) light can be boosted to above 1V so that the charge injection is increased. The proposed chip adopts the 32-phase divisional power supply scheme (DPSS) to reduce the required supply current and thus the required area of the PV cells. The proposed chip is designed and fabricated in 180-nm CMOS technology and post-processed with image sensor biocompatible IrOx electrodes and silicone packaging. From the electrical measurement results, the measured stimulation frequency is 28.3 Hz under the equivalent electrode impedance load. The measured maximum output stimulation current is 7.1 μA and the amount of injected charges per pixel is 7.36 nC under image light intensity of 3200 lux and IR light intensity of 100 mW/cm2. The function of the proposed chip has been further validated successfully with the ex vivo experimental results by recording the electrophysiological responses of retinal ganglion cells (RGCs) of retinas from retinal degeneration (rd1) mice with a multi-electrode array (MEA). The measured average threshold injected charge is about 3.97 nC which is consistent with that obtained from the patch clamp recording on retinas from wild type (C57BL/6) mice with a single electrode pair.
关键词： biocompatible package,divisional power supply scheme,multi-electrode array,charge pump,photovoltaic cell
更新于2025-09-11 14:15:04
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Write Energy Reduction for PCM via Pumping Efficiency Improvement
摘要： The emerging Phase Change Memory (PCM) is considered to be a promising candidate to replace DRAM as the next generation main memory due to its higher scalability and lower leakage power. However, the high write power consumption has become a major challenge in adopting PCM as main memory. In addition to the fact that writing to PCM cells requires high write current and voltage, current loss in the charge pumps also contributes a large percentage of high power consumption. The pumping efficiency of a PCM chip is a concave function of the write current. Leveraging the characteristics of the concave function, the overall pumping efficiency can be improved if the write current is uniform. In this article, we propose a peak-to-average (PTA) write scheme, which smooths the write current fluctuation by regrouping write units. In particular, we calculate the current requirements for each write unit by their values when they are evicted from the last level cache (LLC). When the write units are waiting in the memory controller, we regroup the write units by LLC-assisted PTA to reach the current-uniform goal. Experimental results show that LLC-assisted PTA achieved 13.4% of overall energy saving compared to the baseline.
关键词： pumping efficiency,write regrouping,Phase change memory (PCM),charge pump
更新于2025-09-10 09:29:36
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[IEEE 2018 Conference on Precision Electromagnetic Measurements (CPEM 2018) - Paris, France (2018.7.8-2018.7.13)] 2018 Conference on Precision Electromagnetic Measurements (CPEM 2018) - One-Gate Ratchet Single-Electron Pump: Device Failure Mechanisms
摘要： Electrical current standards based on the charge of the electron will become more important after the SI redefinition. Many of the best recent charge pump results have come in the one-gate ratchet pumping mode, but this mode is sometimes difficult to achieve. In this work, we discuss the likely reasons for this difficulty, and ways to overcome the difficulty.
关键词： single-electron metrology,One-gate ratchet charge pump,device failure mechanisms
更新于2025-09-10 09:29:36
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Fully-Integrated Charge Pump Design Optimization for Above-Breakdown Biasing of Single-Photon Avalanche Diodes in 0.13-μm CMOS
摘要： A design methodology for an area-optimized integrated charge pump is described suitable for on-chip high-voltage reverse bias of single-photon avalanche diodes (SPADs). The high-voltage generation block is implemented in a general-purpose 0.13-μm CMOS process and is capable of generating a maximum regulated output voltage of 17.7 V from an input of 1.8 V. An ON–OFF regulation scheme with dynamic charging and discharging capability of the charge pump provides fast recovery of the output bias voltage during SPAD transients, where overshoot and undershoot must both be corrected during active quench and reset. Following a SPAD avalanche current pulse, the measured transient recovery time is 500 ns from a 150-mV overshoot and a 500-mV undershoot to reach 99% of steady-state output. The implemented SPAD bias generation system occupies 0.175-mm2 chip area, without requiring an off-chip load capacitor.
关键词： Single-photon avalanche diode,charge pump,high-voltage generation,SPAD
更新于2025-09-09 09:28:46