- 标题
- 摘要
- 关键词
- 实验方案
- 产品
-
An FPGA-Oriented Algorithm for Real-Time Filtering of Poisson Noise in Video Streams, with Application to X-Ray Fluoroscopy
摘要： In this paper we propose a new algorithm for real-time ?ltering of video sequences corrupted by Poisson noise. The algorithm provides effective denoising (in some cases overcoming the ?ltering performances of state-of-the-art techniques), is ideally suited for hardware implementation, and can be implemented on a small ?eld-programmable gate array using limited hardware resources. The paper describes the proposed algorithm, using X-ray ?uoroscopy as a case study. We use IIR ?lters for time ?ltering, which largely simpli?es hardware cost with respect to previous FIR ?lter-based implementations. A conditional reset is implemented in the IIR ?lter, to minimize motion blur, with the help of an adaptive thresholding approach. Spatial ?ltering performs a conditional mean to further reduce noise and to remove isolated noisy pixels. IIR ?lter hardware implementation is optimized by using a novel technique, based on Steiglitz–McBride iterative method, to calculate ?xed-point ?lter coef?cients with minimal number of nonzero elements. Implementation results using the smallest StratixIV FPGA show that the system uses only, at most, the 22% of the resources of the device, while performing real-time ?ltering of 1024 × 1024@49fps video stream. For comparison, a previous FIR ?lter-based implementation, on the same FPGA, in the same conditions and constraints (1024 × 1024@49fps), requires the 80% of the logic resources of the FPGA.
关键词： Poisson noise,X-ray video?uoroscopy processing,Field-programmable gate array (FPGA),IIR ?ltering,IIR ?lter design,Real-time video ?ltering
更新于2025-09-23 15:22:29
-
HLS Based Approach to Develop an Implementable HDR Algorithm
摘要： Hardware suitability of an algorithm can only be verified when the algorithm is actually implemented in the hardware. By hardware, we indicate system on chip (SoC) where both processor and field-programmable gate array (FPGA) are available. Our goal is to develop a simple algorithm that can be implemented on hardware where high-level synthesis (HLS) will reduce the tiresome work of manual hardware description language (HDL) optimization. We propose an algorithm to achieve high dynamic range (HDR) image from a single low dynamic range (LDR) image. We use highlight removal technique for this purpose. Our target is to develop parameter free simple algorithm that can be easily implemented on hardware. For this purpose, we use statistical information of the image. While software development is verified with state of the art, the HLS approach confirms that the proposed algorithm is implementable to hardware. The performance of the algorithm is measured using four no-reference metrics. According to the measurement of the structural similarity (SSIM) index metric and peak signal-to-noise ratio (PSNR), hardware simulated output is at least 98.87 percent and 39.90 dB similar to the software simulated output. Our approach is novel and effective in the development of hardware implementable HDR algorithm from a single LDR image using the HLS tool.
关键词： system on chip,high-dynamic range image,low-dynamic range image,field-programmable gate array,high-level synthesis
更新于2025-09-23 15:22:29
-
[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Industrial Production and Field Evaluation of Transparent Electrodynamic Screen (EDS) Film for Water-Free Cleaning of Solar Collectors
摘要： Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than simple technology scaling. Quantitative effects of Moore’s Law have driven qualitative changes in FPGA architecture, applications and tools. As a consequence, FPGAs have passed through several distinct phases of development. These phases, termed ‘‘Ages’’ in this paper, are The Age of Invention, The Age of Expansion and The Age of Accumulation. This paper summarizes each and discusses their driving pressures and fundamental characteristics. The paper concludes with a vision of the upcoming Age of FPGAs.
关键词： commercialization,programmable logic,Moore’s Law,Application-specific integrated circuit (ASIC),economies of scale,field-programmable gate array (FPGA),industrial economics
更新于2025-09-23 15:19:57
-
Gaussian random number generator: Implemented in FPGA for quantum key distribution
摘要： Quantum key distribution is the process of using quantum communication to establish a shared key between two parties. It has been demonstrated the unconditional security and effective communication of quantum communication system can be guaranteed by an excellent Gaussian random number (GRN) generator with high speed and an extended random period. In this paper, we propose to construct the Gaussian random number generator by using field‐programmable gate array (FPGA), which is able to process large data in high speed. We also compare three algorithms of GRN generation: Box‐Muller algorithm, polarization decision algorithm, and central limit algorithm. We demonstrate that the polarization decision algorithm implemented in FPGA requires less computing resources and also produces a high‐quality GRN through the null hypothesis test.
关键词： field‐programmable gate array,numerical modeling,quantum key distribution,Gaussian random numbers
更新于2025-09-19 17:15:36
-
Phase-locking particle image velocimetry measurement of unsteady flow behaviors: Online dynamic mode decomposition using field-programmable gate array
摘要： A novel online dynamic mode decomposition (DMD) approach using a field-programmable gate array (FPGA), which takes full advantage of the DMD to extract multiple unsteady events and the FPGA system for signal sampling and fast computation, was developed for phase-locking particle image velocimetry (PIV) measurements of unsteady flow behaviors. The turbulent separated and reattaching flow around a finite blunt plate with a length-to-height-ratio L/D = 6.0 was examined to demonstrate this novel approach. The wall-pressure field and the velocity field were measured using arrayed microphones and the conventional planar PIV setup, respectively. Offline DMD analysis of the wall-pressure fluctuation field was first used to identify the dominant modes corresponding to the energetically unsteady events. For each mode, the eigenmode and its mode coefficient reflected the spatial footprint pattern and temporal strength of the unsteady event, respectively. Next, trained machine learning of the mode coefficient was used to establish a phase prediction strategy. Finally, in the online analysis, the relevant eigenmode was cast into the FPGA device to serve as the reference mode for reconstruction with the sampled wall-pressure data, determining the phase signal to fire the PIV setup. High-resolution spatiotemporal evolutions of the dominant flow structures (i.e., the flapping separation bubble, the impinging leading-edge vortex, and the trailing-edge vortex street) were separately assembled. Further measurements demonstrated a clear panoramic view of the synchronous behavior of the enlarging separation bubble and the impinging leading-edge vortex. The proposed online FPGA-DMD approach can serve as a sophisticated strategy for phase-locking PIV measurements of unsteady flow behaviors.
关键词： phase-locking,dynamic mode decomposition,unsteady flow,particle image velocimetry,field-programmable gate array
更新于2025-09-19 17:15:36
-
[IEEE 2019 International Multi-Conference on Industrial Engineering and Modern Technologies (FarEastCon) - Vladivostok, Russia (2019.10.1-2019.10.4)] 2019 International Multi-Conference on Industrial Engineering and Modern Technologies (FarEastCon) - Energy Surface of Pit-Patterned Templates for Growth of Space-Arranged Arrays of Quantum Dots a?? Molecular Dynamics Calculations Using High-Efficiency Algorithms
摘要： With its reprogrammability, low design cost, and increasing capacity, field-programmable gate array (FPGA) has become a popular design platform and a target for infringement. Currently available intellectual property (IP) protection solutions are usually limited to protect single FPGA configurations and require permanent secret key storage in the FPGA. In addition, they cannot provide a commercially popular pay-per-device licensing solution. In this paper, we propose a novel IP protection mechanism to restrict IP’s execution only on specific FPGA devices in order to efficiently protect IPs from being cloned, copied, or used with unauthorized integration. This mechanism can also enforce the pay-per-device licensing, which enables the system developers to purchase IPs from the core vendors at the low price based on usage instead of paying the expensive unlimited IP license fees. In our proposed binding-based mechanism, FPGA vendors embed into each enrolled FPGA device with a physical unclonable function (PUF) customized for FPGAs; IP vendors embed augmented finite-state machines (FSM) into the original IPs such that the FSM can be activated by the PUF responses from the FPGA device. We propose protocols to lock and unlock FPGA IPs, demonstrate how PUF can be embedded onto FPGA devices, and analyze the security vulnerabilities of our PUF-FSM binding method. We implement a 128-bit delay-based PUF on 28-nm FPGAs with only 258 RAM-lookup tables and 256 flipflops. The PUF responses are unique and reliable against environment changes. We also synthesize a variety of FSM benchmark circuits. On large benchmarks, the average timing overhead is 0.64% and power overhead in 0.01%.
关键词： hardware metering,intellectual property (IP) protection,finite state machine (FSM),Binding,physical unclonable functions (PUFs),field-programmable gate array (FPGA)
更新于2025-09-19 17:13:59
-
[IEEE 2019 16th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON) - Pattaya, Chonburi, Thailand (2019.7.10-2019.7.13)] 2019 16th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON) - The Designation of the Lightning Protection for the Photovoltaic Module by using the Protective Angle Method
摘要： In this paper, a new and efficient methodology is proposed to quickly and precisely evaluate the power consumption and performance of wireless communication base-band systems implemented in field-programmable gate arrays (FPGAs). As the complexity of such systems is still growing, being able to estimate both power and performance of a design has become a major issue. FPGA devices constitute a promising technology in this highly constrained context. However, to respect their power budget, designers need to explore the design space very soon in the design process. This is performed prior to any implementation. Based on the innovative definition of a scenario, which enables comparison among wireless communication applications in a formal manner, each parameter can be evaluated to meet the power-performance tradeoff. In this paper, the proposed methodology is realized in two steps using a low-level characterization process and high-level system modeling. Another major contribution consists in considering components’ time activity to refine power estimations results. We demonstrate the effectiveness of the proposed methodology throughout several domain-specific use cases, with a focus on hardware base-band processing in the wireless communication domain. As compared with current low-level FPGAs vendor tools, an important speedup factor is obtained, and a maximal relative error lower than 5% is reached.
关键词： system modelling,SystemC,Wireless communication,field programmable gate array,power consumption
更新于2025-09-19 17:13:59
-
Free Space Optical Communication (System Design, Modeling, Characterization and Dealing with Turbulence) || 5. Low power and compact RSM and neural-controller design for beam wandering mitigation with a horizontal-path propagating Gaussian-beam wave: focused beam case
摘要： Beam wander on the detector plane is one of the main causes of major power loss which severely degrades the performance of Free Space Optical (FSO) links. Confronted with this big problem, designing a suitable controller to compensate beam wandering at a fast rate so as to increase beam stability becomes significant. This chapter presents an investigation of the performance of two types of controller designed for increasing the stability of the beam on the detector plane under dynamic disturbances. The first design is based on Taguchi’s method: Response Surface Model (RSM) controller while the second is the Artificial Neural Network (ANN) method (neural-controller). These controllers process the beam spot information and generate the necessary outputs to mitigate beam wandering, so as to perfectly couple the Power In the Bucket (PIB): receiver aperture, into the detector. Pipelined-parallel architecture for both controllers are proposed and developed in a Field Programmable Gate Array (FPGA). The implementation of these two candidate controllers is described in detail as installed at the receiver station. Evidence of the suitability and the effectiveness of the proposed controllers in terms of prediction exactness, prediction error, reduction of beam wander, response to impulse and effective scintillation index are provided through experimental results from the FSO link established for the horizontal range of 0.5 km at an altitude of 15.25 m.
关键词： Artificial Neural Network (ANN),Field Programmable Gate Array (FPGA),beam wander,Free Space Optical (FSO) links,Response Surface Model (RSM)
更新于2025-09-12 10:27:22
-
An Advanced 100-Channel Readout System for Nuclear Imaging
摘要： Reading out from large-scale silicon photomultiplier (SiPM) arrays is a fundamental technical obstacle blocking the application of revolutionary SiPM technologies in nuclear imaging systems. Typically, it requires using dedicated application-specific integrated circuits (ASICs) that need a long iterative process, special expertise, and tools to develop. The pico-positron emission tomography (Pico-PET) electronics system is an advanced 100-channel readout system based on 1-bit sigma–delta modulation and a field-programmable gate array (FPGA). It is compact (6 × 6 × 0.8 cm3 in size), consumes little power (less than 3W), and is constructed with off-the-shelf low-cost components. In experimental studies, the Pico-PET system demonstrates excellent and consistent performance. In addition, it has some unique features that are essential for nuclear imaging systems, such as its ability to measure V–I curves, breakdown voltages, and the dark currents of 100 SiPMs accurately, simultaneously, and in real time. The flexibility afforded by FPGAs allows multiple-channel clustering and intelligent triggering for different detector designs. These highly sought-after features are not offered by any other ASICs and electronics systems developed for nuclear imaging. We conclude that the Pico-PET electronics system provides a practical solution to the long-standing bottleneck problem that has limited the development of potentially advanced nuclear imaging technology using SiPMs.
关键词： silicon photomultiplier (SiPM),readout electronics,Field-programmable gate array (FPGA),nuclear imaging,sigma–delta modulation
更新于2025-09-10 09:29:36
-
Efficient Energy Management System for Solar Energy
摘要： Solar power is the major renewable energy source opted by developing countries as stand-alone/Grid enabled system. Industries and educational institutions are opting for solar energy to combat power crisis. This paper proposes knowledge based, self configurable, smart controller to efficiently use solar energy according to load, under frequent grid failure environment. It is enabled with fault identification and isolation. Extension to higher power capacity is easily achieved with plug and play mechanism. Proposed control architecture is implemented using Field Programmable Gate Array (FPGA), that supports modular level implementation with well defined interfaces for each sub-system. It can be used with low power as well as high power photo-voltaic system. Efficiency of the proposed architecture is demonstrated for the photo-voltaic system installed in educational institution.
关键词： Field Programmable Gate Array,Standalone system,Pulse width modulation,Photo-voltaic system
更新于2025-09-09 09:28:46