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High-Voltage AlInGaN LED Chips
摘要： A high-voltage light-emitting diode (LED) flip chip based on an AlInGaN heterostructure is developed and fabricated. The LED flip chip consists of 16 elements connected in series, each of which is a conventional LED. The chip with a total area of 1.25 × 1.25 mm is intended for a working current of 20 mA and a forward voltage of 48 V. To improve the current-distribution uniformity over the active region of the chip elements and to minimize the losses of the element area occupied by the n-type contact, the n-type contact pads in them are arranged inside the p-type contact region due to the two-level metallization layout with an intermediate insulating layer of dielectric. The arrangement topology of the contact pads is developed using numerical simulation. An increase in the quantum efficiency of the chip is provided by the application of combinations of metals with a high reflectance at the LED emission wavelength, which are used when fabricating n- and p-type contacts as well as current-carrying strips.
关键词： light-emitting diode,flip-chip design,LED chip,gallium nitride,high-voltage chip
更新于2025-09-12 10:27:22
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[IEEE 2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition - Warsaw (2017.9.10-2017.9.13)] 2017 21st European Microelectronics and Packaging Conference (EMPC) & Exhibition - High voltage WireLED powered directly by mains 230 Volts
摘要： for the need of energy saving, LEDs are taking more and more space in lighting modules. Moreover, LEDs add several applications to the lighting function, smartness, dimming, bio photonic applications, a lot of fields that none former light sources could reach [1]. The manufacturers of course must keep the target of making a device compatible with the standards in terms of safety first, but moreover the compactness and reliability with the well-known thermal issues, depending on the wall plug efficiency of the component. In order to manage all the mentioned points, as often, packaging is the key point if one seeks to maximize the lifetime of a LED based luminaire. Indeed, because they are aware of the existing technologies and comparison thanks to quick information available on the Internet, today’s customers cannot accept to pay a more expensive light source that have lower performance than the former lighting technologies [2]. The paper that we propose describes the manufacturing and the packaging of a LED device made from GaN micro wires compatible with direct mains powering on the 230 Volts-50 Hz network. We show why the heterogeneous stack to manufacture the lighting device, coupled with the high voltage input is a big challenge. Once the front side wire LEDs patterning is finished, many technological steps remain in order to deliver a WLP assembly ready for the back-end assembly process. The carrier bonding, the back side processing for N and P contacts patterning, the hybridization by flip chip technology using copper bumps or solder balls are roughly described with the related issues. Final thermal and electrical characterizations were conducted to evaluate the performances of the high voltage LED device.
关键词： High voltage,Packaging,Bump,WireLED,IMS,Flip Chip,Trench
更新于2025-09-12 10:27:22
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[IEEE 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Las Vegas, NV, USA (2019.5.28-2019.5.31)] 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Laser-Induced Trench Design, Optimisation and Validation for Restricting Capillary Underfill Spread in Advanced Packaging Configurations
摘要： Spreading of flip-chip capillary underfill material into regions of other components can complicate their assembly and/or integrity. We propose a novel, cost-effective means to control this spread through the use of thin, linear trenches of controlled depth on solder mask surfaces. To optimally exploit this method, an in-depth study is conducted to understand the underlying mechanism. Using high resolution 3D optical profilometry, trench profile is first correlated to key laser process parameters. Trench profiles are then evaluated by means of a custom designed underfill loading test vehicle in order to determine their relative effectiveness. Characterization of both the trench and restricted underfill profiles demonstrate correlation to the Gibbs’ inequality relationship for surface tension. A trench profile is identified for chip assembly that balances high underfill restricting capacity with acceptable width and depth to suit the specificity of a substrate solder mask. The restriction of underfill spreading is then investigated in the critical dispense region of a Package on Package (PoP) application comprising stringent spacing criteria between a flip chip device and proximal BGA connections. Using trenches proposed by the laser parameter study and placed as close as 0.7 mm from chip edge, successful dispense processing and subsequent underfill flow bounding are demonstrated. Finally, underfill spread and fillet formation in the presence of trenches on the non-dispense (exit) sides of a chip assembly is investigated to determine the limits of trench proximity to chip edge. Control of underfill spread is demonstrated at trench lines as close as 0.2 mm from the chip edge on the exit sides. Using comparable samples with unrestricted underfill flow, a reduction of 0.4 mm in underfill spread on each exit side is observed. Considering the possible contact angle of the underfill at the trench edge, one can model how close the trench lines should be placed to achieve a fillet height satisfying the design specifications.
关键词： ultraviolet laser,flip chip,heterogeneous integration,system in package,capillary underfill
更新于2025-09-12 10:27:22
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P‐9.3: The representation of monochromatic blue Micro‐LED arrays with 1984 ppi
摘要： Blue InGaN/GaN Micro-LED arrays based on silicon and sapphire substrates were fabricated respectively. The LED chips with 12.8 μm pixel pitch share a common n contactor in a 960*540 LED array. The driving current for a single LED chip with 8 μm mesa reaches as large as 20 mA, which indicates its current density is much larger than that of LEDs even in high power lighting application. Meanwhile, the reverse leakage current of a single 8μm size LED chip under -5V bias is below 10 pA, which falls within the range of a normal leakage current level for InGaN/GaN LED. The heat pressing bonding process between LED array and test backplane was also carried out for I-V-L test. The test results of LED arrays were presented.
关键词： Micro display,Flip-chip bonding,Micro-LED
更新于2025-09-12 10:27:22
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[IEEE 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Las Vegas, NV, USA (2019.5.28-2019.5.31)] 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Flip-Chip III-V-to-Silicon Photonics Interfaces for Optical Sensor
摘要： We demonstrate flip-chip solder assembly of InP chips on Silicon-Photonic (Si-Ph) substrates aimed at high volume manufacturing using typical microelectronic lead-free solders. In our show-case application, an InP die is both a light source and a detector in an integrated optical methane gas sensor that operates near 1.6mm. For high-resolution laser absorption spectroscopy sensing, a single-mode tunable laser is desired. We create an external cavity laser with InP as optical gain, butt-coupled to a Si-Ph external cavity, which incorporates the laser’s frequency selective elements. For minimal reflection at the InP-Si interface, waveguides are angled to the facet, an index-matching medium is applied between the mating surfaces, and an anti-reflection coating designed for the index-matching medium is applied to the optical coupling facet of InP chip. Sub-micron alignment accuracy is obtained without high-accuracy assembly tooling. Lithographically defined alignment features on both InP and Si components allow reproducible high-accuracy alignment. Interface throughput loss were measured to be as low as 1.4 dB, and interface reflections are more than 30dB smaller than main signal beams.
关键词： flip-chip assembly,Silicon & III-V photonics,heterogeneous assembly,solder reflow
更新于2025-09-11 14:15:04
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Development and optimization of the laser-assisted bonding process for a flip chip package
摘要： In a ?ne pitch ?ip chip package, a laser-assisted bonding (LAB) technology has recently been developed to overcome several reliability and throughput issues in the conventional mass re?ow (MR) and thermal compression bonding technology. This study investigated the LAB process for a ?ip chip package with a copper (Cu) pillar bump using numerical heat transfer and thermo-mechanical analysis. During the LAB process, the temperature of the silicon die was uniform across the entire surface and increased to 280 (cid:3)C within a few seconds; this was high enough to melt the solder. The heat in the die was quickly conducted to the substrate through the Cu pillar bumps. Meanwhile, the substrate temperature was low and remained constant. Therefore, a stable solder interconnection was quickly achieved with minimal stress and thermal damage to the package. The substrate thickness, the number of Cu bumps, and the bonding stage temperature were found to be important factors affecting the heat transfer behavior of the package. The temperature of the die decreased when a thinner substrate, a higher number of Cu bumps, and a lower bonding stage temperature were used. If the temperature of the die was not suf?ciently high, insuf?cient heat was transferred to the solder to melt it, resulting in incomplete solder joint formation. Thermo-mechanical analysis also showed that the LAB process produced lower warpage and thermo-mechanical strain than the conventional MR process. These results indicated that a LAB process using a selective local heating method would be bene?cial in reducing thermo-mechanical stress and increasing throughput for the ?ne pitch ?ip chip packages.
关键词： Laser-assisted bonding,Copper pillar bump,Thermo-mechanical analysis,Flip chip package,Heat transfer
更新于2025-09-11 14:15:04
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Optical admittance method for light-matter interaction in lossy planar resonators
摘要： Advanced optoelectronic simulation models are needed to study and optimize emerging photonic devices such as thin-film solar cells, lasers, and light-emitting diodes (LEDs). In particular, better tools are required for self-consistent modeling of coupled electrical and optical systems. The recently introduced quantized fluctuational electrodynamics (QFED) and the associated interference-exact radiative transfer equations have been developed for this purpose, but their use is in part complicated by the need to calculate the full dyadic Green’s functions. To make QFED and the underlying physical quantities more accessible for new device studies, we introduce a directly usable method where Green’s functions are obtained through optical admittances. The optical admittances can be solved analytically for piecewise-homogeneous layer structures and selected graded-index profiles, and numerically for arbitrary position-dependent refractive index profiles using well-known techniques. The solutions enable direct construction of the dyadic Green’s functions and all the related optical quantities. To give examples of the general applicability of the method, we calculate the local and nonlocal optical densities of states for selected devices, including GaN-based flip-chip LEDs and vertical-cavity surface-emitting lasers. Using only the rather simple framework presented in this paper, one can analyze energy transport in a wide range of planar photonic devices accurately without additional difficulties or inputs from external solvers.
关键词： dyadic Green’s functions,quantized fluctuational electrodynamics,GaN-based flip-chip LEDs,optoelectronic simulation models,photonic devices,optical admittances,vertical-cavity surface-emitting lasers
更新于2025-09-09 09:28:46
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Flip-Chip Bonding Fabrication Technique
摘要： Military systems, outer space exploration and even in medical diagnosis and treatment used magnetic field detection. Low magnetic field detection is particularly important in tracking of magnetic. Traditional magnetometer tends to be bulky that hinders its inclusion into micro-scaled environment. This concern has brought the magnetometer into the trend of device miniaturization. Miniaturized magnetometer is usually fabricated using conventional microfabrication method particularly surface micromachining in which micro structures are built level by level starting from the surface of substrates upwards until completion of final structure. Although the miniaturization of magnetometer has been widely researched and studied, the process however is not. Thus, the process governing the fabrication technique is studied in this paper. Conventional method of fabrication is known as surface micromachining. Besides time consuming, this method requires many consecutive steps in fabrication process and careful alignment of patterns on every layer which increase the complexity. Hence, studies are done to improve time consuming and reliability of the microfabrication process. The objective of this research includes designing micro scale magnetometer and complete device fabrication processes. A micro-scale search coil magnetometer of 15 windings with 600μm thickness of wire and 300μm distance between each wire has been designed.
关键词： Surface Micromachining,Fabrication Technique,Micro magnetometer,Flip-Chip Bonding
更新于2025-09-09 09:28:46
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[IEEE 2018 48th European Microwave Conference (EuMC) - Madrid, Spain (2018.9.23-2018.9.27)] 2018 48th European Microwave Conference (EuMC) - A Scalable Dual-Polarized 256-Element Ku-Band SATCOM Phased-Array Transmitter with 36.5 dBW EIRP Per Polarization
摘要： This paper presents a Ku-band dual-polarized transmit phased-array with 256-elements spaced λ/2 apart at 14 GHz in the x and y directions. The design is based on 64 silicon quad-core transmit chips with 8 channels, and these chips are used to feed a 2x2 quad antennas with dual polarizations. The output P1dB per channel is 12 dBm at 14 GHz. The silicon core-chips are flipped directly on a 12-layer low-cost printed circuit board (PCB) with stacked patch antennas and Wilkinson dividers. The 256-element phased-array results in a measured EIRP of 64.5 dBm and 66.5 dBm at P1dB and Psat, respectively, at normal incidence, per polarization. Measured patterns show a scan region of ±60° in E- and H-planes with low sidelobes and near-ideal patterns. The design achieves a cross polarization level < -27 dB up to ±45° and < -23 dB at ±60° scan angle, in both planes. The array is scalable to allow the construction of large-scale phased-arrays (1024 elements or more). To our knowledge, this represents state-of-the-art in Ku-band transmit phased-arrays in terms of integration level making it suitable for a low-cost mobile Ku-band SATCOM terminal.
关键词： silicon,phased arrays,transmit,SATCOM,antenna,beamforming,Ku-Band,PCB,14 GHz,SiGe,flip-chip
更新于2025-09-04 15:30:14
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An X-ray TES Detector Head Assembly for a STEM–EDS System and Its Performance
摘要： A detector head for an energy-dispersive X-ray spectroscopy (EDS) for a scanning transmission electron microscope (STEM) was designed, fabricated, and tested. A 64-pixel TES X-ray microcalorimeter and 64 SQUID array amplifiers (SAAs) are mounted on a detector head which is cooled to about 100 mK. The body of the detector head is a copper rod of about 1 cm2 cross section and 10 cm length with 3 cm cubic structure at the bottom. The TES microcalorimeter is mounted at the top of the rod while the SAAs are mounted on the four side surfaces of the cubic structure. In order to reduce the number of wire bondings, we adopted a flip-chip bonding for the SAAs. In order to reduce the stress imposed on the flip-chip bondings due to the difference in the linear thermal expansion of the SAA chip and the mounting surfaces, we mounted the SAAs and connectors to the room-temperature electronics on sapphire circuit board and mounted the SAAs and connectors using a superconducting flip-chip bonding technology. Then, both the TES and the sapphire circuit board were mounted on the rod and are connected to the print circuit like superconducting wires, which are created on the multiple surfaces of the rod, with Al wire bondings. We reduced the number of wire bondings from 768 to 256. The yield of the flip-chip bonding was not perfect but relatively high. We installed the detector head in the STEM EDS system, confirmed that the energy resolution and counting requirements, (cid:2)E < 10 eV with 5 kcps were fulfilled.
关键词： EDS,TES,Superconducting flip-chip bonding,STEM
更新于2025-09-04 15:30:14