A D-band Multiplier-based OOK Transceiver with Supplementary Transistor Modeling in 65-nm Bulk CMOS Technology

摘要： A D-band on-off keying (OOK) transceiver chipset is fabricated in a 65-nm bulk CMOS technology as a low-cost and highly-integrative solution to short-distance wireless connectivity. Supplementary transistor modeling is performed for accurate circuit design at mm-wave frequencies. To overcome low transistor fmax and reduce DC power consumption, the transmitter employs a frequency-multiplier-based architecture with no power amplifier. The receiver adopts a non-coherent architecture consisting of a DC-coupled three-stage differential amplifier and an envelope detector. The OOK transmitter exhibits a measured output power of -9.8 dBm and on-off level difference of 13.2 dB at 134.1 GHz. The receiver shows a measured average responsivity of 4.1 kV/W and a noise equivalent power of 211.4 pW/Hz1/2 over all D-band frequencies. The DC power consumption of the transmitter and receiver are 76 mW and 32.5 mW, respectively. The transceiver is tested in both on-chip loopback and air-channel configurations, and demonstrates data transmission up to 10 Gbps and 2 Gbps at a distance of 0.03 m, respectively.