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[IEEE 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) - Kolkata, India (2019.8.29-2019.8.31)] 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) - Effect of I Shaped Periodic Structures over Collinear Arms of 150 Degree Bend Substrate Integrated Waveguide
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： parallel computing,GPU,LDPC decoders,reconfigurable computing,high-level synthesis,CPU,LDPC codes
更新于2025-09-23 15:21:01
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A Reconfigurable and Extendable Single-Inductor Single-Path Three-Switch Converter for Indoor Photovoltaic Energy Harvesting
摘要： This article proposes a single-path three-switch (1P3S) single-inductor dual-input dual-output (SIDIDO) converter to manage power among a photovoltaic (PV) module, battery, and load for indoor PV energy harvesting. For low duty-cycle applications, the 1P3S converter increases efficiency in the PV-to-battery-to-load path by eliminating inductor-sharing power switches. This article also proposes a reconfigurable controller to achieve reconfigurability and extendibility that the 1P3S converter can be reconfigured as a dual-path three-switch (2P3S) SIDIDO converter, combined as a dual-path six-switch (2P6S) SIDIDO converter, or extended as a paralleled-1P3S converter for high energy efficiency in various applications with different PV and load power profiles. To identify each converter’s advantageous applications, the efficiencies of the 1P3S, reconfigured 2P3S, and combined 2P6S converters were analyzed under dynamic PV and load powers. The chip is fabricated in the 0.5-μm CMOS process with a 1.24-mm2 chip area. The measured peak efficiencies for the 1P3S, 2P3S, and 2P6S converters are 95.0%, 95.2%, and 90.0%, respectively, while the measured quiescent currents are 210, 130, and 140 nA, respectively. Compared with the state-of-the-art 2P3S and 2P6S converters, the reconfigured 2P3S and combined 2P6S converters with the proposed IC, respectively, achieve higher efficiency through appropriate switch sizes and ON-time optimizations.
关键词： Dual-path six-switch (2P6S),single-path three-switch (1P3S),dual-path three-switch (2P3S),maximum power point tracking (MPPT),photovoltaic (PV) energy harvesting,energy efficiency,reconfigurable controller
更新于2025-09-23 15:21:01
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Beam Steering of a Terahertz Semi Bow Tie Antenna Using Parasitic Graphene Ribbons
摘要： In this paper, a reconfigurable beam-scanning planar antenna is proposed in terahertz frequencies. The presented structure consists of a semi bow tie antenna surrounded by circularly arranged parasitic pieces of graphene. The performance of the proposed antenna is investigated considering three different states where a PEC ground plane and a graphene ground layer with chemical potentials 0 (mode A) and 1 (mode B) are utilized at the bottom of the substrate. The proposed antenna is designed for utilization at a specific frequency of 1.2 THz in all these three states. The achieved antenna boresight and radiation pattern are altered through changing the conductivity of parasitic graphene elements and ground plane, which is obtained by controlling the corresponding chemical potential of the graphene segments. In addition, the parasitic graphene elements, located around the antenna, provide a high degree of freedom for altering the radiation pattern and antenna boresight. The parasitic elements operate as directors in modes A and B, whereas they act as reflectors in PEC ground state. Moreover, a high beam steering capability is obtained as chemical potentials of graphene elements are allocated between 0 and 1, whereas a PEC ground layer is employed at the bottom of the antenna. It should be noted that the gain and front-to-back ratio of the antenna are controlled using different chemical potentials of the graphene elements. A wide range of scan angles allocated between 0 and 180°, and toward the left and right directions in constant φ plane is achieved for the designed antenna.
关键词： Terahertz,Graphene,Reconfigurable,Beam steering,Antenna
更新于2025-09-23 15:21:01
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[IEEE 2018 International Conference Laser Optics (ICLO) - St. Petersburg (2018.6.4-2018.6.8)] 2018 International Conference Laser Optics (ICLO) - Compact CPA Laser System Based on Yb Fiber Seeder and Yb:YAG Amplifier
摘要： A coarse-grained reconfigurable processing unit (RPU) consisting of multi-functional processing elements (PEs) interconnected by an area-efficient line-switched mesh connect (LSMC) routing is implemented on a die in TSMC 65 nm LP1P8M CMOS technology. A hierarchical configuration context (HCC) organization scheme is proposed to reduce the implementation overhead and the energy dissipation spent on fast reconfiguration. The proposed RPU is integrated into two system-on-a-chips (SoCs), targeting multiple-standard video decoding. The high-performance chip, comprising two RPU processors (named REMUS_HPP), can decode H.264 video streams at 30 frames per second (fps) under 200 MHz. REMUS_HPP achieves a 25% performance gain over the XPP-III reconfigurable processor with only 280 mW power consumption, resulting in a improvement on energy efficiency. The other chip (named REMUS_LPP), targeting low power applications, integrates only one RPU processor. REMUS_LPP can decode H.264 video streams at 35fps with 24.5 mW under 75 MHz, achieving a 76% reduction in power dissipation and improvement on energy efficiency compared with the ADRES reconfigurable processor.
关键词： reconfigurable computing,video decoding,Coarse-grained reconfigurable array
更新于2025-09-23 15:19:57
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Improved Maximum Power Point Tracking of Partially Shaded PV Arrays Using Particle Swarm Optimization with Zone Initialization
摘要： A coarse-grained reconfigurable processing unit (RPU) consisting of multi-functional processing elements (PEs) interconnected by an area-efficient line-switched mesh connect (LSMC) routing is implemented on a die in TSMC 65 nm LP1P8M CMOS technology. A hierarchical configuration context (HCC) organization scheme is proposed to reduce the implementation overhead and the energy dissipation spent on fast reconfiguration. The proposed RPU is integrated into two system-on-a-chips (SoCs), targeting multiple-standard video decoding. The high-performance chip, comprising two RPU processors (named REMUS_HPP), can decode H.264 video streams at 30 frames per second (fps) under 200 MHz. REMUS_HPP achieves a 25% performance gain over the XPP-III reconfigurable processor with only 280 mW power consumption, resulting in a improvement on energy efficiency. The other chip (named REMUS_LPP), targeting low power applications, integrates only one RPU processor. REMUS_LPP can decode H.264 video streams at 35fps with 24.5 mW under 75 MHz, achieving a 76% reduction in power dissipation and improvement on energy efficiency compared with the ADRES reconfigurable processor.
关键词： reconfigurable computing,video decoding,Coarse-grained reconfigurable array
更新于2025-09-23 15:19:57
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[IEEE 2019 6th International Conference on Electric Vehicular Technology (ICEVT) - Bali, Indonesia (2019.11.18-2019.11.21)] 2019 6th International Conference on Electric Vehicular Technology (ICEVT) - Experimental Method for Improving Efficiency on Photovoltaic Cell Using Passive Cooling and Floating Method
摘要： Software-defined radio (SDR) allows the unprecedented levels of flexibility by transitioning the radio communication system from a rigid hardware platform to a more user-controlled software paradigm. However, it can still be time-consuming to design and implement such SDRs as they typically require thorough knowledge of the operating environment and a careful tuning of the program. In this paper, our contribution is the design of a bidirectional transceiver that runs on the commonly used USRP platform and implemented in MATLAB using standard tools like MATLAB Coder and MEX to speed up the processing steps. We outline strategies on how to create a state-action-based design, wherein the same node switches between transmitter and receiver functions. Our design allows the optimal selection of the parameters toward meeting the timing requirements set forth by various processing blocks associated with a differential binary phase shift keying physical layer and CSMA/CA/ACK MAC layer, so that all the operations remain functionally compliant with the IEEE 802.11b standard for the 1 Mb/s specification. The code base of the system is enabled through the Communications System Toolbox and incorporates channel sensing and exponential random back-off for contention resolution. The current work provides an experimental testbed that enables the creation of new MAC protocols starting from the fundamental IEEE 802.11b standard. Our design approach guarantees consistent performance of the bi-directional link, and the three-node experimental results demonstrate the robustness of the system in mitigating packet collisions and enforcing fairness among nodes, making it a feasible framework in higher layer protocol design.
关键词： Software defined radio,IEEE 802.11b,exponential random back-off,MEX,CSMA/CA/ACK,reconfigurable computing,energy detection
更新于2025-09-23 15:19:57
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[IEEE 2019 IEEE 8th International Conference on Advanced Optoelectronics and Lasers (CAOL) - Sozopol, Bulgaria (2019.9.6-2019.9.8)] 2019 IEEE 8th International Conference on Advanced Optoelectronics and Lasers (CAOL) - Hybrid lasers using CMOS compatible nanostructures
摘要： Battery packs with a large number of battery cells are becoming more and more widely adopted in electronic systems, such as robotics, renewable energy systems, energy storage in smart grids, and electronic vehicles. Therefore, a well-designed battery pack is essential for battery applications. In the literature, the majority of research in battery pack design focuses on battery management system, safety circuit, and cell-balancing strategies. Recently, the reconfigurable battery pack design has gained increasing attentions as a promising solution to solve the problems existing in the conventional battery packs and associated battery management systems, such as low energy efficiency, short pack lifespan, safety issues, and low reliability. One of the most prominent features of reconfigurable battery packs is that the battery cell topology can be dynamically reconfigured in the real-time fashion based on the current condition (in terms of the state of charge and the state of health) of battery cells. So far, there are several reconfigurable battery schemes having been proposed and validated in the literature, all sharing the advantage of cell topology reconfiguration that ensures balanced cell states during charging and discharging, meanwhile providing strong fault tolerance ability. This survey is undertaken with the intent of identifying the state-of-the-art technologies of reconfigurable battery as well as providing review on related technologies and insight on future research in this emerging area.
关键词： Reconfigurable battery pack,SOC,battery management system,energy storage system
更新于2025-09-23 15:19:57
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Modeling Electrical Switching of Nonvolatile Phase-Change Integrated Nanophotonic Structures with Graphene Heaters
摘要： Progress in integrated nanophotonics has enabled large-scale programmable photonic integrated circuits (PICs) for general-purpose electronic-photonic systems on a chip. Relying on the weak, volatile thermo-optic or electro-optic effects, such systems usually exhibit limited reconfigurability along with high energy consumption and large footprints. These challenges can be addressed by resorting to chalcogenide phase-change materials (PCMs) such as Ge2Sb2Te5 (GST) that provide substantial optical contrast in a self-holding fashion upon phase transitions. However, current PCM-based integrated photonic applications are limited to single devices or simple PICs due to the poor scalability of the optical or electrical self-heating actuation approaches. Thermal-conduction heating via external electrical heaters, instead, allows large-scale integration and large-area switching, but fast and energy-efficient electrical control is yet to show. Here, we model electrical switching of GST-clad integrated nanophotonic structures with graphene heaters based on the programmable GST-on-silicon platform. Thanks to the ultra-low heat capacity and high in-plane thermal conductivity of graphene, the proposed structures exhibit a high switching speed of ~80 MHz and high energy efficiency of 19.2 aJ/nm3 (6.6 aJ/nm3) for crystallization (amorphization) while achieving complete phase transitions to ensure strong attenuation (~6.46 dB/μm) and optical phase (~0.28 π/μm at 1550 nm) modulation. Compared with indium tin oxide and silicon p-i-n heaters, the structures with graphene heaters display two orders of magnitude higher figure of merits for heating and overall performance. Our work facilitates the analysis and understanding of the thermal-conduction heating-enabled phase transitions on PICs and supports the development of the future large-scale PCM-based electronic-photonic systems.
关键词： graphene,nonvolatile,reconfigurable photonics,phase-change materials,silicon photonics,integrated nanophotonic structures
更新于2025-09-23 15:19:57
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - InGaN Quantum Dots for Intermediate Band Solar Cells
摘要： A novel simple approach to the verification process for millimeter-wave vector network analyzer waveguide calibration is reported using a single reconfigurable component verification kit. Conventional techniques require multiple verification components and these only exist commercially for operation up to 110 GHz. At millimeter-wave frequencies, the use of multiple components can lead to significant errors due to imperfections in waveguide flange misalignments during the multiple component connections. The reconfigurable component is designed so that its electrical properties can be changed quickly to a broad range of predetermined values without introducing additional errors due to changes in flange alignment. Once connected, the component can be reconfigured to introduce relative changes in the reflected and transmitted signals. For millimeter-wave metrology, where mechanical precision is of paramount importance, this single-component verification approach represents an attractive solution. A proof-of-concept verification process is described, based on full-wave electromagnetic modeling, hardware implementation, and validation measurements using standard WR-15 waveguide (50–75 GHz).
关键词： verification,millimeter-wave,Measurement,vector network analyzer (VNA),reconfigurable,rectangular waveguide
更新于2025-09-23 15:19:57
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[IEEE 2019 IEEE Sustainable Power and Energy Conference (iSPEC) - Beijing, China (2019.11.21-2019.11.23)] 2019 IEEE Sustainable Power and Energy Conference (iSPEC) - Accurate Short-term Forecasting for Photovoltaic Power Method Using RBM Combined LSTM-RNN Structure with Weather Factors Quantification
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： LDPC codes,high-level synthesis,CPU,parallel computing,LDPC decoders,reconfigurable computing,GPU
更新于2025-09-23 15:19:57