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[IEEE 2019 21st International Conference on Transparent Optical Networks (ICTON) - Angers, France (2019.7.9-2019.7.13)] 2019 21st International Conference on Transparent Optical Networks (ICTON) - Chiral Quantum Photonics in Semiconductor Nano-Photonic Waveguides
摘要： Reconfigurable architectures can bring unique capabilities to computational tasks. They offer the performance and energy efficiency of hardware with the flexibility of software. In some domains, they are the only way to achieve the required, real-time performance without fabricating custom integrated circuits. Their functionality can be upgraded and repaired during their operational lifecycle and specialized to the particular instance of a task. We survey the field of reconfigurable computing, providing a guide to the body-of-knowledge accumulated in architecture, compute models, tools, run-time reconfiguration, and applications.
关键词： Field programmable gate arrays,reconfigurable computing,reconfigurable logic,reconfigurable architectures
更新于2025-09-19 17:13:59
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[IEEE 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Munich, Germany (2019.6.23-2019.6.27)] 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Refuting Observer-Independence in Quantum Theory
摘要： Physical unclonable functions (PUFs) are increasingly used for authentication and identification applications as well as the cryptographic key generation. An important feature of a PUF is the reliance on minute random variations in the fabricated hardware to derive a trusted random key. Currently, most PUF designs focus on exploiting process variations intrinsic to the CMOS technology. In recent years, progress in emerging nanoelectronic devices has demonstrated an increase in variation as a consequence of scaling down to the nanoregion. To date, emerging PUFs with nanotechnology have not been fully established, but they are expected to emerge. Initial research in this area aims to provide security primitives for emerging integrated circuits with nanotechnology. In this paper, we review emerging nanotechnology-based PUFs.
关键词： Physical unclonable functions,reconfigurable PUF,nanotechnology,hardware security,nanoelectronic devices,strong PUF
更新于2025-09-19 17:13:59
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[IEEE 2019 16th China International Forum on Solid State Lighting & 2019 International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS) - Shenzhen, China (2019.11.25-2019.11.27)] 2019 16th China International Forum on Solid State Lighting & 2019 International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS) - Violet Chip Excited White LEDs for Sun-Like Lighting and Horticulture Lighting
摘要： In this work, facing pressure from both the increasing vulnerability to single event effects (SEEs) and design constraints of the power consumption, we have proposed a Coarse-Grained Reconfigurable Architecture (CGRA) processor. Our goal is to translate a user programmable redundancy to a guide for balancing energy consumption on the one hand and the reliability requirements on the other. We designed software (SW) and hardware (HW) approaches, coordinating them closely to achieve this purpose. The framework provides several user-assignable patterns of redundancy and the hardware modules to interpret well these patterns. A first version prototype processor, with the name EReLA (Explicit Redundancy Linear Array) has been implemented and manufactured with a CMOS technology. Stress tests based on alpha particle irradiation were conducted to verify the tradeoff between the robustness and the power efficiency of the proposed schemes.
关键词： fault tolerance,Data flow computing,redundancy,reconfigurable architectures
更新于2025-09-19 17:13:59
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[IEEE 2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall) - Xiamen, China (2019.12.17-2019.12.20)] 2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall) - Microwave Approach to Study Resonant Features of All-dielectric Metasurfaces
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： parallel computing,GPU,LDPC decoders,reconfigurable computing,high-level synthesis,CPU,LDPC codes
更新于2025-09-19 17:13:59
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Deep Learning Enabled Optimization of Downlink Beamforming Under Per-Antenna Power Constraints: Algorithms and Experimental Demonstration
摘要： Physical unclonable functions (PUFs) are increasingly used for authentication and identification applications as well as the cryptographic key generation. An important feature of a PUF is the reliance on minute random variations in the fabricated hardware to derive a trusted random key. Currently, most PUF designs focus on exploiting process variations intrinsic to the CMOS technology. In recent years, progress in emerging nanoelectronic devices has demonstrated an increase in variation as a consequence of scaling down to the nanoregion. To date, emerging PUFs with nanotechnology have not been fully established, but they are expected to emerge. Initial research in this area aims to provide security primitives for emerging integrated circuits with nanotechnology. In this paper, we review emerging nanotechnology-based PUFs.
关键词： Physical unclonable functions,reconfigurable PUF,strong PUF,nanoelectronic devices,nanotechnology,hardware security
更新于2025-09-19 17:13:59
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[IEEE 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) - St. Petersburg and Moscow, Russia (2020.1.27-2020.1.30)] 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) - Viability Analysis of Large Photovoltaic Power Plants as a Solution of Power Shortage in Iraq
摘要： In this work, facing pressure from both the increasing vulnerability to single event effects (SEEs) and design constraints of the power consumption, we have proposed a Coarse-Grained Reconfigurable Architecture (CGRA) processor. Our goal is to translate a user programmable redundancy to a guide for balancing energy consumption on the one hand and the reliability requirements on the other. We designed software (SW) and hardware (HW) approaches, coordinating them closely to achieve this purpose. The framework provides several user-assignable patterns of redundancy and the hardware modules to interpret well these patterns. A first version prototype processor, with the name EReLA (Explicit Redundancy Linear Array) has been implemented and manufactured with a m CMOS technology. Stress tests based on alpha particle irradiation were conducted to verify the tradeoff between the robustness and the power efficiency of the proposed schemes.
关键词： reconfigurable architectures,redundancy,Data flow computing,fault tolerance
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Theoretical study of the MAPbI <sub/>3</sub> /SnO <sub/>2</sub> interface band offset in perovskite solar cells considering mobile ions
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： LDPC codes,high-level synthesis,CPU,parallel computing,LDPC decoders,reconfigurable computing,GPU
更新于2025-09-19 17:13:59
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Reconfigurable H‐plane waveguide phase shifters prototyping with additive manufacturing at K‐band
摘要： This work presents the design and manufacturing of a K-band reconfigurable phase shifter completely implemented in waveguide technology for reduced insertion loss, good matching, and large phase shifting range. The device is based on the combination of a short slot coupler and two tunable reactive loads implemented as a section of short-circuited waveguide where an adjustable metallic post is inserted. Three prototypes of this design have been manufactured using different techniques (conventional computer numerical control machining, a low-cost fused filament fabrication technique and direct metal laser sintering) in order to assess its performance for different applications. The prototypes have been characterized experimentally and the achieved results are evaluated and compared. The proposed phase shifter, since it is fully developed in waveguide technology, eliminates the need of adding transitions to planar structures in order to integrate lumped components like pin diodes or varactors. Therefore, this device has a great potential in high-power beam steering phased arrays.
关键词： reconfigurable,selective laser sintering,additive manufacturing,waveguide,fused filament fabrication,phase shifter
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE International Symposium on Phased Array System & Technology (PAST) - Waltham, MA, USA (2019.10.15-2019.10.18)] 2019 IEEE International Symposium on Phased Array System & Technology (PAST) - Non-Uniform Steerable Leaky-Wave Antenna Based on Substrate Integrated Waveguide
摘要： In this paper, we introduce a novel electronically steerable antenna. The proposed design is a substrate integrated waveguide based quasi-uniform leaky-wave antenna. Introducing sets of switches over the slots and biasing them non-uniformly enables the scanning capability. Due to non-uniform distribution of the bias voltage of the switches, we achieve large variation in the radiation patterns. The center frequency is chosen as 28.5 GHz to accommodate 5G wireless networks. The width, length, and height of the antenna are 24 mm, 68 mm, and 0.3 mm, respectively. Scanning capability, compactness, and simplicity of the proposed structure makes it a suitable candidate for 5G wireless networks.
关键词： antenna,varactor,slot,reconfigurable
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Flexible silicon heterojunction solar cells on 40 ?μm thin substrates
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： LDPC codes,high-level synthesis,CPU,parallel computing,LDPC decoders,reconfigurable computing,GPU
更新于2025-09-19 17:13:59