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Nonlinear Electrothermal Model for Investigating Transient Temperature Responses of a Through-Silicon Via Array Applied With Gaussian Pulses in 3-D IC
摘要： In this paper, a through-silicon via (TSV) array under Gaussian pulse is studied comprehensively with a rigorous consideration of its electrothermal characteristics. To enhance the computational efficiency and reduce the memory cost, we develop a unified radial point interpolation method (RPIM) to handle these TSV electrothermal coupling problems. The comparison between the results of the proposed formulas and fine-grid finite-element method (FEM) shows that the RPIM has a very high accuracy and reduces computational time by up to 88% in comparison with the fine-grid FEM. The transient temperature responses are studied in detail for three layouts of single-layered TSV arrays with different silicon dioxide layer thicknesses and areas enclosed by TSVs. Furthermore, the two-layered TSV array structure including microbumps and RDLs is simulated electrothermally to verify the scalability of this method. Our work demonstrated the capability of addressing a large number of TSV arrays and the proposed method enables faster and more accurate electrothermal design of TSV-based 3-D ICs.
关键词： transient temperature,Electrothermal,through silicon vias (TSV),radial point interpolation method (RPIM),TSV array,Gaussian pulse
更新于2025-09-19 17:15:36
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Effects of Copper Migration on the Reliability of Through-Silicon Via (TSV)
摘要： Non-destructive electrical characterization was performed to detect copper migration in a degraded through-silicon via structure after various stressing conditions such as elevated temperature exposure, temperature cycling and electrical biasing. They were performed either independently or as a combination with electrical bias for comparison. Variations in the electrical characteristics reflect the presence of copper. The electrical characteristics were also able to monitor the transport of copper ions from an applied electric field. Physical failure analysis was performed to verify the presence of migrated copper, correlating to the changes observed during electrical measurement. With this understanding, reliability assessments become possible where this paper seeks to value add to verify the influence of Cu migration on the conduction mechanism and TDDB lifetime, understanding.
关键词： Electrical characterization,Through-silicon vias,Reliability testing,Dielectric breakdown,Copper
更新于2025-09-10 09:29:36
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Fabrication and Optimization of High Aspect Ratio Through-Silicon-Vias Electroplating for 3D Inductor
摘要： In this study, the ?lling process of high aspect ratio through-silicon-vias (TSVs) under dense conditions using the electroplating method was ef?ciently achieved and optimized. Pulsed power was used as the experimental power source and the electroplating solution was prepared with various additive concentrations. Designed control variable experiments were conducted to determine the optimized method. In the control variable experiments, the relationship of multiple experimental variables, including current density (0.25–2 A/dm2), additive concentration (0.5–2 mL/L), and different shapes of TSVs (circle, oral, and square), were systematically analyzed. Considering the electroplating speed and quality, the in?uence of different factors on experimental results and the optimized parameters were determined. The results showed that increasing current density improved the electroplating speed but decreased the quality. Additives worked well, whereas their concentrations were controlled within a suitable range. The TSV shape also in?uenced the electroplating result. When the current density was 1.5 A/dm2 and the additive concentration was 1 mL/L, the TSV ?lling was relatively better. With the optimized parameters, 500-μm-deep TSVs with a high aspect ratio of 10:1 were fully ?lled in 20 h, and the via density reached 70/mm2. Finally, optimized parameters were adopted, and the electroplating of 1000-μm-deep TSVs with a diameter of 100 μm was completed in 45 h, which is the deepest and smallest through which a three-dimensional inductor has ever been successfully fabricated.
关键词： electroplating,high aspect ratio,through-silicon-vias (TSV),three-dimensional (3D) inductor,control variable method
更新于2025-09-09 09:28:46
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HIGH FREQUENCY ELECTRICAL CHARACTERIZATION OF 3D SIGNAL/GROUND THROUGH SILICON VIAS
摘要： 3D integration using through-silicon-vias (TSVs) is gaining considerable attention due to its superior packaging e?ciency resulting in higher functionality, improved performance and a reduction in power consumption. In order to implement 3D chip designs with TSV technology, robust TSV electrical models are required. Speci?cally, due to the increase of signal speeds into the gigahertz (GHz) spectrum, a high frequency electrical characterization best describes TSV behavior. In this letter, 5 × 50 μm TSVs are manufactured using a via-mid integration scheme and characterized using S-parameters up to 65 GHz. At 50 GHz, the measured attenuation constant is 0.35 dB/via with a time delay of 0.7 ps/via.
关键词： time delay,3D integration,attenuation constant,through-silicon-vias (TSVs),S-parameters,high frequency electrical characterization
更新于2025-09-09 09:28:46
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A multi-step etch method for fabricating slightly tapered through-silicon vias based on modified Bosch process
摘要： In this paper, a multi-step etching method based on Bosch process was investigated to fabricate a slightly tapered via. The diameter of vias was scaled from 40 to 100 lm. Isotropic etching step was added into Bosch process to control the angle of the tapered vias. The slope angle could be adjusted by changing the time settings of isotropic etching step. The in?uence of the platen temperature was also studied. The passivation and etching steps are extremely sensitive to temperature. Silicon grass could be formed at low temperature. The two different processes of isotropic SF6 etching and Cl2/HBr etching were also compared. The wrinkles and cracks were observed on the surface after treatment with isotropic SF6 etching. The Cl2/HBr etching method is much better for removing the scallops.
关键词： platen temperature,Cl2/HBr etching,slightly tapered through-silicon vias,multi-step etch method,SF6 etching,isotropic etching,modified Bosch process
更新于2025-09-04 15:30:14
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Bottom-Up Copper Filling of Large Scale Through Silicon Vias for MEMS Technology
摘要： An electrodeposition process for void-free bottom-up ?lling of sub-millimeter scale through silicon vias (TSVs) with Cu is detailed. The 600 μm deep and nominally 125 μm diameter metallized vias were ?lled with Cu in less than 7 hours under potentiostatic control. The electrolyte is comprised of 1.25 mol/L CuSO4 – 0.25 mol/L CH3SO3H with polyether and halide additions that selectively suppress metal deposition on the free surface and side walls. A brief qualitative discussion of the procedures used to identify and optimize the bottom-up void-free feature ?lling is presented.
关键词： Cu filling,MEMS technology,through silicon vias,electrodeposition
更新于2025-09-04 15:30:14