- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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[IEEE 2018 International Conference on Microwave and Millimeter Wave Technology (ICMMT) - Chengdu, China (2018.5.7-2018.5.11)] 2018 International Conference on Microwave and Millimeter Wave Technology (ICMMT) - A 300GHz Monolithic Integrated Amplifier in 0.5-μm InP Double Heterojunction Bipolar Transistor Technology
摘要： We present a compact, 6-stage terahertz monolithic integrated circuit (TMIC) amplifier with an operating frequency of 275-310GHz, formed by common-base configured 0.5 um InP Double Heterojunction Bipolar Transistor (DHBT) and a multilayer thin-film microstrip (TFM) wiring environment. The amplifier small signal gain exhibits >7.4dB at 300GHz. The peak gain is 12.5dB at 280GHz. This is the first time reported InP DHBT TMIC amplifier operating in H-band employing TFM in china. The total size of this 6-stage amplifier is only 1.7 mm ╳0.9 mm.
关键词： thin-film microstrip (TFM),Indium phosphide (InP),H-band,Amplifier,Heterojunction bipolar transistors (HBTs),Terahertz monolithic integrated circuit (TMIC)
更新于2025-09-23 15:22:29
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[IEEE 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) - Tallinn, Estonia (2018.10.30-2018.10.31)] 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) - Application Specific Integrated Gate-Drive Circuit for Driving Self-Oscillating Gallium Nitride & Logic-Level Power Transistors
摘要： Wide bandgap power semiconductors are key enablers for increasing the power density of switch-mode power supplies. However, they require new gate drive technologies. This paper examines and characterizes a fabricated gate-driver in a class-E resonant inverter. The gate-driver’s total area of 1.2 mm2 includes two high-voltage transistors for gate-driving, integrated complementary metal-oxide-semiconductor (CMOS) gate-drivers, high-speed floating level-shifter and reset circuitry. A prototype printed circuit board (PCB) was designed to assess the implications of an electrostatic discharge (ESD) diode, its parasitic capacitance and package bondwire connections. The parasitic capacitance was estimated using its discharge time from an initial voltage and the capacitance is 56.7 pF. Both bondwires and the diode’s parasitic capacitance is neglegible. The gate-driver’s functional behaviour is validated using a parallel LC resonant tank resembling a self-oscillating gate-drive. Measurements and simulations show the ESD diode clamps the output voltage to a minimum of ?2 V.
关键词： Self-oscillating,Analog integrated circuit,gate-driver,ASIC
更新于2025-09-23 15:22:29
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Research on Image Smoothing Diffusion Model with Gradient and Curvature Features
摘要： In this paper, two image smoothing models are proposed for the visual inspection of high-density flexible IC package substrates with strict requirements on line-width and line distance which are applied to the de-noising of high-density flexible IC package substrate images. First of all, the two models proposed in this paper combines the level set curvature feature of the image with gradient threshold, using more abundant second-order differential information as the detection factor to remove noise in image. Secondly, theoretical analysis shows that the de-noised image obtained by the two models proposed can retain more detailed texture information and edge information of the original image. What is more, the experimental analysis shows that the proposed models have the highest structural similarity and peak signal-to-noise ratio, and have a relatively high edge-preserving index and the lowest mean squared error compared with other models. In particular, the de-noised image through Model 1 has the highest structural similarity and peak signal to noise ratio, as well as the lowest mean squared error. The de-noised image through Model 2 has a relatively high edge retention index. The methods proposed in this paper can effectively remove the noise of the image of the high-density flexible IC package substrate, and can retain the original details and edges information of the image.
关键词： Image de-noising,Flexible integrated circuit substrate image,Gradient,Curvature
更新于2025-09-23 15:22:29
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Design of a Compact GaN MMIC Doherty Power Amplifier and System Level Analysis With X-Parameters for 5G Communications
摘要： This paper presents a monolithic microwave integrated circuit Doherty power amplifier (DPA) operating at sub-6 GHz for 5G communication applications by a 0.25-μm gallium nitride high-electron mobility transistor process. A compact impedance inverter and output matching of the DPA are achieved using a transmission line network and shunt capacitors. Also, the size ratio of power cells in the main and auxiliary amplifiers is optimized for a high efficiency at output power backoff (OPBO). The measured peak output power (Pout) and the 1-dB compression point (P1 dB) are 38.7 and 32.1 dBm, respectively, at 5.9 GHz. The power-added efficiency at 6-dB OPBO is up to 49.5%. Without digital predistortion (DPD), the DPA can deliver an average Pout of 23.5 dBm with error vector magnitude (EVM) <?28 dB and 21.5 dBm with EVM <?32 dB for 64-quadrature amplitude modulation (QAM) and 256-QAM signals, respectively. The measured X-parameters are employed to further investigate the DPA nonlinear characteristics and verify the accuracy of conventionally used power amplifier characterization/measurement methods for system-level design and testing applications. The simulated results based on the X-parameters also indicate that the average output power can be enhanced up to 25.7 dBm with DPD for 256-QAM.
关键词： 5G communication,monolithic microwave integrated circuit (MMIC),X-parameters,power-added efficiency (PAE),power amplifier (PA),Doherty,gallium nitride (GaN)
更新于2025-09-23 15:21:21
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Development of multi-function digital optoelectronic integrated sensor
摘要： A multi-function optoelectronic integrated sensor based on the 180 nm standard CMOS process for ambient light detection and position sensing is proposed. The monolithic opto-electronic integrated receiver chip is made of a photodetector (PD), a trans-impedance amplifier (TIA), an analog to digital converter (ADC), and a driving circuit of light-emitting diode (LED). A prototype of the sensor has be implemented and tested, and the opto-electronic model of PD is built and simulated for OEIC Co-design. The sensor has been demonstrated a linear detection of the ambient light with intensity between 0 lux and 10000 lux and the detection precision was measured to be 8.79 lux. The precision of proximity distance detection reaches 0.1mm. Simple recognition of object moving direction can be realized. The sensor can be widely used in smart phones, portable wearable devices and other intelligent product terminals.
关键词： CMOS integrated circuit,position sensing,integrated optoelectronic sensor,ambient light,mixed-signal circuits
更新于2025-09-23 15:21:01
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Designing low power and high contrast ratio all-optical NOT logic gate for using in optical integrated circuits
摘要： In this paper, a new design of all-optical NOT logic gate is proposed. In this structure, a photonic crystal nano-resonator and three waveguides are used. The nano-resonator is formed by removing two dielectric rods. The contrast ratio for the proposed NOT logic gate is 20.75?dB. The maximum response time and the rate of sending information equal to 0.466?ps and 2.145?Tbit/s, respectively. In addition, very low power consumption, small size, and simple design are the main features of this logic gate. These features allow the designed structure to be used in all-optical switches. To accomplish this, two types of logic gates placement alongside each other in the optical integrated circuits are proposed and investigated. In both types, the logic gates are tested for single use and simultaneous use, and the accuracy of the performance and effect of each on the other is measured. The results clearly show that the two logic gates, along with each other, have acceptable perfor- mance and can easily be used in the optical integrated circuit.
关键词： Nano-resonator,Optical integrated circuit,All-optical NOT logic gate,Response time,Photonic crystal
更新于2025-09-23 15:21:01
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[IEEE 2018 International Conference on Optical MEMS and Nanophotonics (OMN) - Lausanne (2018.7.29-2018.8.2)] 2018 International Conference on Optical MEMS and Nanophotonics (OMN) - Digital Silicon Photonic MEMS Phase-Shifter
摘要： We report on a 4-bit digital silicon photonic MEMS phase-shifter with sub-microsecond switching time and low power consumption (< 10 uW). The device consists of 4 digitally switched phase-shifting units, which in total enable phase shift from (cid:2)(cid:2)(cid:1)/8 to 15pi/8 in increments of (cid:2)(cid:1)/8.
关键词： Silicon Photonic MEMS,Adiabatic Coupler,Phase Control,Photonic Integrated Circuit,Optical Switch
更新于2025-09-23 15:21:01
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[IEEE 2019 Compound Semiconductor Week (CSW) - Nara, Japan (2019.5.19-2019.5.23)] 2019 Compound Semiconductor Week (CSW) - Room-Temperature Electrically Pumped InP-based $1.3\boldsymbol{\mu} \mathbf{m}$ Quantum Dot Laser on on-axis (001) Silicon
摘要： We present a method for quantifying a risk for killer defects at layer level and estimating yield for substrate packages using information from design ?les. To calculate risk ranks and predicted yield, we de?ne a risk distance that is a key parameter extracted from designs using image processing techniques. In order to validate our model, we analyze two different designs, each having multiple layers, and compare with data from baseline lots. It is shown that there is an inverse correlation between risk layer ranks and yield. Estimated yield based on our model is compared with baseline yield for four layers of the second design. The model-to-baseline yield difference is less than 1% for three layers we tested.
关键词： yield estimation,assembly,circuit analysis,metrology sampling,Yield prediction,integrated circuit packaging
更新于2025-09-23 15:19:57
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[IEEE 2019 Compound Semiconductor Week (CSW) - Nara, Japan (2019.5.19-2019.5.23)] 2019 Compound Semiconductor Week (CSW) - Effect of Annealing on The Bottom Cell in GaInP/GaAs/GaInNAsSb Triple Junction Solar Cells by MBE/MOCVD Hybrid Growth
摘要： We present a method for quantifying a risk for killer defects at layer level and estimating yield for substrate packages using information from design ?les. To calculate risk ranks and predicted yield, we de?ne a risk distance that is a key parameter extracted from designs using image processing techniques. In order to validate our model, we analyze two different designs, each having multiple layers, and compare with data from baseline lots. It is shown that there is an inverse correlation between risk layer ranks and yield. Estimated yield based on our model is compared with baseline yield for four layers of the second design. The model-to-baseline yield difference is less than 1% for three layers we tested.
关键词： yield estimation,assembly,circuit analysis,metrology sampling,Yield prediction,integrated circuit packaging
更新于2025-09-23 15:19:57
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Industrial Production and Field Evaluation of Transparent Electrodynamic Screen (EDS) Film for Water-Free Cleaning of Solar Collectors
摘要： Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than simple technology scaling. Quantitative effects of Moore’s Law have driven qualitative changes in FPGA architecture, applications and tools. As a consequence, FPGAs have passed through several distinct phases of development. These phases, termed ‘‘Ages’’ in this paper, are The Age of Invention, The Age of Expansion and The Age of Accumulation. This paper summarizes each and discusses their driving pressures and fundamental characteristics. The paper concludes with a vision of the upcoming Age of FPGAs.
关键词： commercialization,programmable logic,Moore’s Law,Application-specific integrated circuit (ASIC),economies of scale,field-programmable gate array (FPGA),industrial economics
更新于2025-09-23 15:19:57