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oe1(光电查) - 科学论文

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  • Enhancing electrostatic coupling in silicon quantum dot array by dual gate oxide thickness for large-scale integration

    摘要： We propose a structure with word/bit line control for a two-dimensional quantum dot array, which allows random access for arbitrary quantum dots with a small number of control signals. To control multiple quantum dots with a single signal, every quantum dot should have a wide operating voltage allowance to overcome the property variations. We fabricate two-dimensional quantum dot arrays using silicon-complementary-metal-oxide-semiconductor technology with an alternating dual-standard gate oxide thickness. The quantum dots are designed to have an allowable operating voltage window of 0.2 V to control the number of electrons, which is a window one order of magnitude wider than that of previous works. The proposed structure enables both easy fabrication and operation for multiple quantum dots and will pave the way for practical use of large-scale quantum computers.

    关键词： electrostatic coupling,dual gate oxide thickness,quantum dot array,large-scale integration,silicon-complementary-metal-oxide-semiconductor technology

    更新于2025-09-23 15:19:57

  • Variance Analysis in 3-D Integration: A Statistically Unified Model With Distance Correlations

    摘要： Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design ?ow requires the partitioning of the netlist between the tiers. This paper presents the variability analysis of circuits partitioned into different levels. A comparison among local and global variations effects on ring oscillators (ROs) and SRAM is demonstrated. The across-chip variations and correlation range are shown as a critical point for the 3-D very large-scale integrated circuits, where the local variability is dominant. The correlations between devices due to the distances or the allocation into different tiers are directly taken into account in the SPICE model due to a statically uni?ed model applied to 3-D circuits based on Monte Carlo simulations. Design wise, the 3-D integration can further decrease the circuit variability as shown in RO output frequency and SRAM static noise margin.

    关键词： across-chip variations (ACVs),variability,3-D very large-scale integration (VLSI),SRAM,noise margins,Monte Carlo (MC),3-D integration

    更新于2025-09-10 09:29:36