[IEEE 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Munich, Germany (2019.6.23-2019.6.27)] 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Plug-and-Play Generation and Manipulation of Squeezing on Chip

摘要： We propose a novel graphic method to enable the analysis of the field-effect transistor (FET) threshold voltage variation (cid:2)Vth due to random telegraph signals in a percolative channel. First, through technology computer-aided design simulation with no percolation, both a minimum (cid:2)Vth and a critical curve in a mloc ? σloc plot are produced. The former constitutes a statistical distribution far away from the conventional log-normal one. In the latter, mloc and σloc are the mean and the standard deviation, respectively, of a well-known normal variable in Mueller–Schulz’s percolation theory. The critical mloc ? σloc curve divides the plot into the allowed region and the forbidden region and will go down with increasing gate size. Then, (cid:2)Vth contours in the allowed region are graphically created. While applying to existing experimental (cid:2)Vth statistical distributions of SiON- and high-k metal gate (HKMG)-scaled FETs, resulting paired mloc and σloc at high (cid:2)Vth remain intact, regardless of gate size or gate stack type. This means that the underlying percolation patterns resemble each other, due to the same manufacturing process used. However, if these paired mloc and σloc fall in the forbidden region, it is the critical mloc ? σloc curve dominating. Application to bias and temperature instability statistical data in literature is straightforwardly well done.