研究目的
Investigating the effects of random telegraph signals on the threshold voltage variation in field-effect transistors using a novel graphic method.
研究成果
The proposed graphic method effectively analyzes random telegraph signal impacts on FET threshold voltage variation, revealing underlying percolation patterns and distinguishing between allowed and forbidden regions in the mloc ? σloc plot. The method's application to experimental data demonstrates its utility in probing process-induced percolation and bias and temperature instability effects, offering insights for future device optimization.
研究不足
The method's applicability is constrained by the need for percolation-free TCAD simulation and the specific conditions under which the experimental data were obtained. Potential areas for optimization include the consideration of bulk trap effects and the adaptation of the method for different gate stack types and sizes.
1：Experimental Design and Method Selection:
A novel graphic method was proposed for analyzing FET threshold voltage variation due to random telegraph signals. Technology computer-aided design (TCAD) simulation was used with no percolation to produce a minimum threshold voltage variation and a critical curve in a mloc ? σloc plot.
2：Sample Selection and Data Sources:
Experimental threshold voltage variation statistical distributions of SiON- and high-k metal gate (HKMG)-scaled FETs were used.
3：List of Experimental Equipment and Materials:
TCAD simulation tools were used with specified gate oxide thickness and interface conditions.
4：Experimental Procedures and Operational Workflow:
The method involved creating threshold voltage variation contours in the allowed region of the mloc ? σloc plot and applying these to experimental data.
5：Data Analysis Methods:
The cumulative distribution function of threshold voltage variation was calculated for sets of mloc and σloc in the allowed region, and comparisons were made with experimental distributions.
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