A Cyclic TDC using Variable Delay Circuit

摘要： A cyclic TDC can be implemented in a small area with high resolution but it takes long conversion time. To reduce a conversion time, we introduce variable delay circuits that can change a delay time of a pulse. We also introduce calibration techniques, an offset cancellation and delay matching, to improve linearity of the TDC. We confirmed through circuit simulation that the proposed circuit achieves a time resolution of 9.38 ps, dynamic range of 18.7 ns, sampling rate of 2 MS/s, and a power consumption of 11 mW at 1.8 V operation.