研究目的
To reduce the conversion time of a cyclic TDC while maintaining high resolution and small area, and to improve its linearity through calibration techniques.
研究成果
The proposed cyclic TDC with variable delay circuits achieves a time resolution of 9.38 ps, dynamic range of ±18.7 ns, sampling rate of 2 MS/s, and power consumption of 11 mW at 1.8 V. Calibration techniques improve linearity, but further work is needed for real-world implementation and handling of element variations.
研究不足
The study is based on simulation only, not physical implementation. Non-ideal conditions show degraded linearity due to delay variations, which may require additional techniques like DWA for improvement. Absolute accuracy calibration is needed for environments with voltage and temperature fluctuations.
1：Experimental Design and Method Selection:
The study proposes a cyclic TDC with variable delay circuits and calibration techniques. Circuit simulations were conducted using Verilog for functional simulation and Spice for analog parts with CMOS
2：18 μm process parameters. Sample Selection and Data Sources:
Not applicable as the study is based on circuit simulation without physical samples.
3：List of Experimental Equipment and Materials:
Simulation tools include Verilog and Spice with CMOS
4：18 μm device parameters. Experimental Procedures and Operational Workflow:
The TDC design involves phase detection, delay control, variable delay circuits, and accumulation. Simulations were performed under different conditions (w/o calibration, ideal, non-ideal) to evaluate performance.
5：Data Analysis Methods:
Analysis includes input-output characteristics, DNL, INL, and comparison with existing cyclic TDCs.
独家科研数据包，助您复现前沿成果，加速创新突破
获取完整内容
