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oe1(光电查) - 科学论文

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出版时间
  • 2018
研究主题
  • contrast stretch
  • CMOS image sensor
  • point-of-care (POC) diagnosis
  • bio-microfluidic imaging
应用领域
  • Optoelectronic Information Science and Engineering
机构单位
  • Xi’an University of Technology
183 条数据
?? 中文（中国） ▾

  • Quantitative Monitoring of Tattoo Contrast Variations after 755-nm Laser Treatments in In Vivo Tattoo Models

    摘要： Laser lights have been used by dermatologists for tattoo removal through photothermal interactions. However, most clinical studies used a visual scoring method to evaluate the tattoo removal process less objectively, leading to unnecessary treatments. This study aimed to develop a simple and quantitative imaging method to monitor the degree of tattoo removal in in vivo skin models. Sprague Dawley rat models were tattooed with four different concentrations of black inks. Laser treatment was performed weekly on the tattoos using a wavelength of 755 nm over six weeks. Images of non-treated and treated samples were captured using the same method after each treatment. The intensities of the tattoos were measured to estimate the contrast for quantitative comparison. The results demonstrated that the proposed monitoring method quantified the variations in tattoo contrast after the laser treatment. Histological analysis validated the significant removal of tattoo inks, no thermal injury to adjacent tissue, and uniform remodeling of epidermal and dermal layers after multiple treatments. This study demonstrated the potential of the quantitative monitoring technique in assessing the degree of clearance level objectively during laser treatments in clinics.

    关键词： laser treatment,CMOS sensor,tattoo model,image contrast

    更新于2025-09-19 17:13:59

  • Laser crystallized low-loss polycrystalline silicon waveguides

    摘要： We report the fabrication of low-loss, low temperature deposited polysilicon waveguides via laser crystallization. The process involves pre-patterning amorphous silicon ?lms to con?ne the thermal energy during the crystallization phase, which helps to control the grain growth and reduce the heat transfer to the surrounding media, making it compatible with CMOS integration. Micro-Raman spectroscopy, Secco etching and X-ray di?raction measurements reveal the high crystalline quality of the processed waveguides with the formation of millimeter long crystal grains. Optical losses as low as 5.3 dB/cm have been measured, indicating their suitability for the development of high-density integrated circuits.

    关键词： CMOS integration,low-loss,laser crystallization,polysilicon waveguides,optical losses

    更新于2025-09-19 17:13:59

  • [IEEE 2019 IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP) - Chennai, India (2019.7.4-2019.7.6)] 2019 IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP) - Improved ANN Model for Predicting the AC Energy Output of a Realistic Photovoltaic Grid Connected PV System

    摘要： A sub-0.5 electron read noise VGA (640H×480V) CMOS image sensor has been integrated in a standard 0.18 μm 4PM CMOS process. The low noise performance is achieved exclusively through circuit optimization without any process refinements. The presented imager relies on a 4T pixel of 6.5 μm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. With a pixel bias of 1.5 μA the sensor chip features an input-referred noise histogram from 0.25 e? rms peaking at 0.48 e? rms. The imager features a full well capacity of 6400 e? and its frame rate can go up to 80 fps. It also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6 e?/s. It is also shown that the implementation of the in-pixel n-well does not impact the quantum efficiency of the pinned photo-diode.

    关键词： image sensor,thick oxide,thin oxide,CIS,thermal noise,1/f noise,low noise,sub-electron,low light,CMOS

    更新于2025-09-19 17:13:59

  • [IEEE 2019 2nd International Conference on High Voltage Engineering and Power Systems (ICHVEPS) - Denpasar, Bali, Indonesia (2019.10.1-2019.10.4)] 2019 2nd International Conference on High Voltage Engineering and Power Systems (ICHVEPS) - IoT Application for On-line Monitoring of 1 kWp Photovoltaic System Based on NodeMCU ESP8266 and Android Application

    摘要： The ?rst quanta image sensor jot with photon counting capability is demonstrated. The low-voltage device demonstrates less than 0.3e- r.m.s. read noise on a single read out without the use of avalanche gain and single-electron signal quantization is observed. A new method for determining read noise and conversion gain is also introduced.

    关键词： low read noise,CMOS image sensor,high conversion gain,quanta image sensor,jot device,photon counting

    更新于2025-09-19 17:13:59

  • [IEEE 2019 Compound Semiconductor Week (CSW) - Nara, Japan (2019.5.19-2019.5.23)] 2019 Compound Semiconductor Week (CSW) - Multi-wavelength DFB laser array in InAs/GaAs quantum dot material epitaxially grown on Silicon

    摘要： A ?rst proof-of-concept mm-sized implantable device using ultrasonic power transfer and a hybrid bi-directional data communication link is presented. Ultrasonic power transfer enables miniaturization of the implant and operation deep inside the body, while still achieving safe and high power levels (100 W to a few mWs) required for most implant applications. The current implant prototype measures 4 mm 7.8 mm and is comprised of a piezoelectric receiver, an IC designed in 65 nm CMOS process and an off-chip antenna. The IC can support a maximum DC load of 100 W for an incident acoustic intensity that is 5% of the FDA diagnostic limit. This demonstrates the feasibility of providing further higher available DC power, potentially opening up new implant applications. The proposed hybrid bi-directional data link consists of ultrasonic downlink and RF uplink. Falling edge of the ultrasound input is detected as downlink data. The implant transmits an ultra-wideband (UWB) pulse sequence as uplink data, demonstrating capability of implementing an energy-ef?cient M-ary PPM transmitter in the future.

    关键词： implantable biomedical devices,active recti?er,mm-sized implants,ultrasonic power transfer,piezoelectric receivers,bi-directional data communication,CMOS,antennas,IMD,AC-DC converter,radio transmitters

    更新于2025-09-19 17:13:59

  • [IEEE 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Rome, Italy (2019.6.17-2019.6.20)] 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - A Compact Octa-band Antenna for Handsets Application

    摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.

    关键词： sub-sampling,analog-to-digital converter (ADC),voltage-domain,All-digital phase-locked loop (AD-PLL),frequency synthesizer,CMOS,low-power

    更新于2025-09-19 17:13:59

  • Design guidelines for edge-coupled waveguide unitravelling carrier photodiodes with improved bandwidth

    摘要： This paper presents a fully synthesizable phase-locked loop (PLL) based on injection locking, with an interpolative phase-coupled oscillator, a current output digital-to-analog converter (DAC), and a fine resolution digital varactor. All circuits that make up the PLL are designed and implemented using digital standard cells without any modification, and automatically Place-and-routed (P&R) by a digital design flow without any manual placement. Implemented in a 65 nm digital CMOS process, this work occupies only 110 μm × 60 μm layout area, which is the smallest PLL reported so far to the best knowledge of the authors. The measurement results show that this work achieves a 1.7 ps RMS jitter at 900 MHz output frequency while consuming 780 μW DC power.

    关键词： standard cell,digital varactor,small area,low power,gated injection,injection-locking,dual loop,PLL,synthesizable,logic synthesis,edge injection,low jitter,PVT,AD-PLL,DAC,CMOS

    更新于2025-09-19 17:13:59

  • [IEEE 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) - Dallas, TX, USA (2019.8.4-2019.8.7)] 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) - A CMOS 256-Pixel Self-Photovoltaics-Powered Subretinal Prosthetic Chip with Wide Image Dynamic Range and Shared Electrodes and Its In Vitro Experimental Results on Rd1 Mice

    摘要： A self-photovoltaics-powered CMOS 256-pixel implantable chip with wide image dynamic range and shared electrodes is proposed and fabricated for subretinal prostheses. The infra-red (IR) light is incident only on photovoltaic cells of the chip whereas the visible light is mainly incident on pixels. The proposed adaptive background cancellation circuit (ABCC) is adopted to increase the image dynamic range so that the subretinal chip can adapt for different surrounding illuminances. Moreover, the bi-directional sharing electrodes (BDSEs) is used to increase electrode size under the same chip area and boost the stimulation charges to 11.4 nC. The functions of the chip have been successfully validated with both electrical measurement and in vitro patch clamp experiments with the retinas of Rd1 mice.

    关键词： subretinal prostheses,CMOS image sensor,implantable chip

    更新于2025-09-19 17:13:59

  • [IEEE 2019 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS) - Metz, France (2019.9.18-2019.9.21)] 2019 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS) - Solar Cell Data Acquisition System

    摘要： The development of two new types of high-density, electroless plated microelectrode arrays for CMOS-based high-sensitivity direct bacteria and HeLa cell counting are presented. For emerging high-sensitivity direct pathogen counting, two technical challenges must be addressed. One is the formation of a bacteria-sized microelectrode, and the other is the development of a high-sensitivity and high-speed amperometry circuit. The requirement for microelectrode formation is that the gold microelectrodes are required to be as small as the target cell. By improving a self-aligned electroless plating technique, the dimensions of the microelectrodes on a CMOS sensor chip in this work were successfully reduced to 1.2 μm × 2.05 μm. This is 1/20th of the smallest size reported in the literature. Since a bacteria-sized microelectrode has a severe limitation on the current flow, the amperometry circuit has to have a high sensitivity and high speed with low noise. In this work, a current buffer was inserted to mitigate the potential fluctuation. Three test chips were fabricated using a 0.6-μm CMOS process: two with 1.2 μm × 2.05 μm 1024 × 1024 and 4 μm × 4 μm (16 × 4) sensor arrays and one with 6-μm × 6-μm (16 × 16) sensor arrays; and the microelectrodes were formed on them using electroless plating. The uniformity among the 1024 × 1024 electrodes arranged with a pitch of 3.6 μm × 4.45 μm was optically verified. For improving sensitivity, the trenches on each microelectrode were developed and verified optically and electrochemically for the first time. Higher sensitivity can be achieved by introducing a trench structure than by using a conventional microelectrode formed by contact photolithography. Cyclic voltammetry (CV) measurements obtained using the 1.2 μm × 2.05 μm 16 × 4 and 6-μm × 6-μm 16 × 16 sensor array with electroless-plated microelectrodes successfully demonstrated direct counting of the bacteria-sized microbeads and HeLa cells.

    关键词： microelectrode array,point-of-care testing,HeLa cells,electroless plating,Bacteria counting,CMOS

    更新于2025-09-19 17:13:59

  • [IEEE 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) - Grenoble, France (2019.4.1-2019.4.3)] 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) - Nanowire & Nanosheet FETs for Ultra-Scaled, High-Density Logic and Memory Applications

    摘要： We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around (GAA) FET devices as promising candidates to obtain a better power-performance metric for logic applications for advanced sub-5nm technology nodes, in comparison to finFETs. In addition, vertical NW/NS GAA FETs appear particularly attractive for enabling highly dense memory cells such as SRAMs (with improved read and write stability), and as the selector devices for ultra-scaled MRAMs with lower energy consumption values. These cells can be manufactured by a cost-effective, co-integration scheme with a finFET or NW/NS FET high-performance logic platform for increased on-chip memory content.

    关键词： lateral and vertical nanowire and nanosheet gate-all-around FETs,memory,CMOS,logic,scaling,MRAM

    更新于2025-09-19 17:13:59