研究目的
Investigating the development of a low-power low-jitter all-digital phase-locked loop (AD-PLL) using a digital sub-sampling architecture for high-performance clocks in the Internet of Things (IoTs).
研究成果
The ADC-based AD-PLL using voltage-domain digitization in a sub-sampling architecture achieves high resolution in phase digitalization, enabling low in-band phase noise and low power consumption. The proposed PLL demonstrates competitive performance with a figure of merit (FoM) of ?242 dB, suggesting its potential for high-performance clock generation in IoT applications.
研究不足
The study is limited by the 65 nm CMOS technology's constraints, including device leakage and low supply voltages, which may affect phase noise and spur performance. Additionally, the digital sub-sampling architecture's effectiveness is primarily demonstrated for integer-N operations, with fractional operations requiring further exploration.
1：Experimental Design and Method Selection:
The study employs an all-digital phase-locked loop (AD-PLL) with voltage-domain digitization using an ADC, avoiding the traditional TDC's resolution and power tradeoff. It includes an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL).
2：Sample Selection and Data Sources:
The experiment is conducted using 65 nm CMOS technology, focusing on achieving low in-band phase noise and RMS jitter at a carrier frequency of 2.2 GHz.
3：2 GHz.
List of Experimental Equipment and Materials:
3. List of Experimental Equipment and Materials: The setup includes a spectrum analyzer (Agilent E4407B) and a signal source analyzer (Agilent E5052B) for evaluation.
4：Experimental Procedures and Operational Workflow:
The proposed PLL's performance is measured in terms of phase noise, jitter, and power consumption, with adjustments made to the variable gain amplifier (VGA) to optimize performance.
5：Data Analysis Methods:
The results are analyzed to compare the proposed ADC-PLL's performance with state-of-the-art integer-N digital PLLs, focusing on phase noise, jitter, and figure of merit (FoM).
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