- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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[IEEE 2018 IEEE 3rd International Conference on Image, Vision and Computing (ICIVC) - Chongqing (2018.6.27-2018.6.29)] 2018 IEEE 3rd International Conference on Image, Vision and Computing (ICIVC) - Software Design of Video Signal Processing Circuit Based on FPGA
摘要： A set of FPGA software system for video signal processing circuit is designed in this paper. The system uses FPGA as the core logic control and uses high speed serial transceiver chip tlk2711 as the interface of data transmission. This paper describes the main components of the software and the realization method of the modular design of FPGA, and gives the simulation waveforms and debug results of the main modules. The test results show that the data transmission interfaces provided by the system have a data rate of 6.4Gbps, which can meet the testing requirements of the satellite camera video processing functions and greatly improve the data transmission rate and accuracy.
关键词： FPGA,CCD,data synthesis,signal processing
更新于2025-09-23 15:23:52
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Development of a new high-speed readout system for SOI pixel detectors
摘要： We are developing a new high-speed readout system for silicon on insulator (SOI) pixel detectors. The SOI detector is a monolithic radiation imaging detector based on a 0.2 μm FD-SOI CMOS process. Previously, we used a Xilinx Virtex-4/5 FPGA readout board for the SOI detector and developed many facilities for this board. However, the Virtex-4/5 FPGA is now obsolete and does not have sufficiently high performance for recent experiments that require more than 1-kHz high-speed imaging with a large number of pixels. Thus, we started to develop a new high-speed readout system using the KC705, which is the evaluation board for the Xilinx Kintex-7 FPGA. We developed a new data acquisition structure that has backward compatibility with the previous environment on this board and implements several functions for practical purposes such as micro Computed Tomography. The transfer speed achieved by the new system is 95.3 fps for a 426k pixel detector in continuous data-taking mode, and 762.5 fps in maximum-speed mode. The details of the new readout system are presented.
关键词： X-ray imaging,SOI,FPGA,DAQ,Pixel detector
更新于2025-09-23 15:23:52
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[IEEE 2018 IEEE 2nd Colombian Conference on Robotics and Automation (CCRA) - Barranquilla, Colombia (2018.11.1-2018.11.3)] 2018 IEEE 2nd Colombian Conference on Robotics and Automation (CCRA) - A proposal for a SoC FPGA-based image processing in RGB-D sensors for robotics applications
摘要： The current robots follow clear, repetitive and logical instructions, but generally, they have problems in managing unstructured environments and reacting dynamically to these. Thus, modern robots require improved vision systems capable of obtaining information about such environments at a high acquisition rate and with high processing speeds. The growing demand for robotic platforms, both industrial and mobile, has greatly boosted the development of advanced vision systems. A weak point of traditional computer vision is that it depends on algorithms executed on a computer or server connected to the robot, often involving the need for high computing resources. Therefore, much of the efforts of the last decades have been focused on the improvement of those algorithms. Nevertheless, when the limit of traditional software processing systems (PCs, microcontrollers and microprocessors) is reached, it is necessary to migrate to a more versatile platform -which generally leads to hardware solutions-. The HW/SW design is possible because of high-frequency bridges between the Hard-Processor System (HPS) and the FPGA. Commonly, the most demanding tasks of the image processing are made in the FPGA, whereas the HPS handles the processed data and performs the high-level control function. This work presents a proposal for HW/SW integration using a SoC FPGA, for the images processing provided by the Intel Realsense?3D camera (an RGB-D sensor). This approach seeks to enhance the streamlining and ?ltering stages to obtain faster results compared to a traditional system.
关键词： SoC FPGA,Intel RealSense R200,image processing,RGB-D
更新于2025-09-23 15:23:52
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[IEEE 2018 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA) - Poznan, Poland (2018.9.19-2018.9.21)] 2018 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA) - Hardware implementation of the Gaussian Mixture Model foreground object segmentation algorithm working with ultra-high resolution video stream in real-time
摘要： In this paper a hardware implementation of the Gaussian Mixture Model algorithm for background modelling and foreground object segmentation is presented. The proposed vision system is able to handle video stream with resolution up to 4K (3840x2160 pixels) and 60 frames per second. Moreover, the constraints caused by memory bandwidth limit are also discussed and a few different solutions to tackle this issue have been considered. The designed modules have been verified on the ZCU102 development board with Xilinx Zynq UltraScale+ MPSoC device. Additionally, the computing performance and power consumption have been estimated.
关键词： FPGA,4K video,background modelling,real-time processing,GPU,Gaussian Mixture Model,foreground object segmentation
更新于2025-09-23 15:23:52
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Frame-based Programming, Stream-Based Processing for Medical Image Processing Applications
摘要： This paper presents and evaluates an approach to deploy image and video processing pipelines that are developed frame-oriented on a hardware platform that is stream-oriented, such as an FPGA. First, this calls for a specialized streaming memory hierarchy and accompanying software framework that transparently moves image segments between stages in the image processing pipeline. Second, we use softcore VLIW processors, that are targetable by a C compiler and have hardware debugging capabilities, to evaluate and debug the software before moving to a High-Level Synthesis flow. The algorithm development phase, including debugging and optimizing on the target platform, is often a very time consuming step in the development of a new product. Our proposed platform allows both software developers and hardware designers to test iterations in a matter of seconds (compilation time) instead of hours (synthesis or circuit simulation time).
关键词： Image processing,FPGA,Medical imaging
更新于2025-09-23 15:23:52
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[IEEE 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Porto, Portugal (2018.10.10-2018.10.12)] 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Real-Time Analysis of Living Biological Cell Activity
摘要： This demo shows a computing system able to process data from electrophysiology cultures in real-time. It is the first one able to identify eventual relationship among living cells from the cell activity signals. The hardware demonstrator is able to acquire data from 64 analog signals sampled at 10kHz, but the computing architecture is flexible enough to provide various number of input electrodes depending of its configuration. Most of the parameters are user definable without reconfiguration to ensure the usability of the system for real-life biology experiment.
关键词： biological cell activity,FPGA,HLS,electrophysiology,spike detection,inter-channel correlation,real-time analysis
更新于2025-09-23 15:23:52
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[IEEE 2018 IEEE International Conference on RFID Technology & Application (RFID-TA) - Macau, Macao (2018.9.26-2018.9.28)] 2018 IEEE International Conference on RFID Technology & Application (RFID-TA) - Alternatives to current RFID chip set market offerings
摘要： There are a large number of RFID chip sets on the market. These chip sets cover the most widely deployed RFID technologies. These chip sets enable the rapid development of RFID readers as well as the inclusion of RFID into other devices. These market offerings frequently require an ancillary microprocessor to undertake the anti-collision algorithm in conjunction with the RFID chip set. These chip sets largely act simply to provide an RF front end with some encoding, decoding, protocol framing and CRC checking to support the overall activity. This paper presents the current state of the RFID chip set market and argues that these offerings fall short of what is required from a genuine RFID solution-on-chip (SoC). Alternatives, including a genuine RFID SoC and dedicated RFID ASIC implementing anti-collision algorithms are proposed.
关键词： FPGA,Anti-collision,ASIC,VHDL,RFID
更新于2025-09-23 15:22:29
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Digital Circuit Methods to Correct and Filter Noise of Nonlinear CMOS Image Sensors
摘要： Nonlinear complementary metal-oxide semiconductor (CMOS) image sensors (CISs), such as logarithmic (log) and linear–logarithmic (linlog) sensors, achieve high/wide dynamic ranges in single exposures at video frame rates. As with linear CISs, fixed pattern noise (FPN) correction and salt-and-pepper noise (SPN) filtering are required to achieve high image quality. This paper presents a method to generate digital integrated circuits, suitable for any monotonic nonlinear CIS, to correct FPN in hard real time. It also presents a method to generate digital integrated circuits, suitable for any monochromatic nonlinear CIS, to filter SPN in hard real time. The methods are validated by implementing and testing generated circuits using field-programmable gate array (FPGA) tools from both Xilinx and Altera. Generated circuits are shown to be efficient, in terms of logic elements, memory bits, and power consumption. Scalability of the methods to full high-definition (FHD) video processing is also demonstrated. In particular, FPN correction and SPN filtering of over 140 megapixels per second are feasible, in hard real time, irrespective of the degree of nonlinearity.
关键词： FPGA,salt-and-pepper noise,digital circuits,real-time processing,fixed pattern noise,CMOS image sensors
更新于2025-09-23 15:22:29
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[IEEE 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Porto, Portugal (2018.10.10-2018.10.12)] 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Low Power Image Processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial Reconfiguration
摘要： The TULIPP project aims to facilitate the development of embedded image processing systems with real-time and low-power constraints. In this paper, several adaptive dynamic runtime techniques for reconfigurable SoCs are described. These methods are used for low power image processing applications on high-performance embedded platforms. Dynamic voltage scaling and dynamic partial reconfiguration target the low-power requirements of the embedded systems while debugging supports the fast development on the hardware side of the system. The proposed techniques were tested and verified using an own developed custom SDSoC image processing library.
关键词： low power,FPGA,image processing,Debugging,Embedded systems,reconfigurable,real-time,Dynamic Voltage Scaling,Dynamic Partial Reconfiguration
更新于2025-09-23 15:22:29
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[IEEE 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Porto, Portugal (2018.10.10-2018.10.12)] 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP) - Hardware-Software Implementation of a SFM Module for Navigation an Unmanned Aerial Vehicles-A Demo
摘要： In this paper the design of an embedded vision system for structure from motion (SFM) computation is presented. The solution allows for scene depth reconstruction based on two consecutive video frames registered by a moving camera. The module is developed for a Xilinx Zynq SoC (System on Chip) device and is divided into a hardware and software part. The programmable logic (PL) is used mainly for detect and match features. Fundamental matrix estimation and triangulation are executed in the processing system (PS – ARM based). The module is dedicated to navigation of unmanned aerial vehicles (UAV) – autonomous flight and landing. The system is adapted to process a 1280x720 pixel video stream @60 frames per second in real-time.
关键词： FPGA,Zynq SoC,structure from motion,real-time video processing,hardware-software systems
更新于2025-09-23 15:22:29