研究目的
To facilitate the development of embedded image processing systems with real-time and low-power constraints by describing adaptive dynamic runtime techniques for reconfigurable SoCs, including dynamic voltage scaling and dynamic partial reconfiguration, and verifying them with a custom SDSoC image processing library.
研究成果
Dynamic voltage scaling and dynamic partial reconfiguration effectively reduce power consumption in image processing applications on FPGAs, with DVS achieving up to 37.6% power reduction and DPR enabling runtime reconfiguration without full resynthesis. Debugging support enhances hardware development. Future work should focus on integrating DVFS, developing custom IP for parallel execution, and applying these techniques to multi-core real-time operating systems.
研究不足
The techniques are implemented on specific hardware (Xilinx Zynq-7000 SoC), limiting generalizability. DVS does not include frequency scaling, which could further optimize power and performance. The debugging system may require additional resources for larger trace windows. Integration of DVS and DPR is complex and not fully combined in this work. Future work is needed for multi-core systems and custom IP for DVFS.
1：Experimental Design and Method Selection:
The study employs dynamic voltage scaling (DVS) and dynamic partial reconfiguration (DPR) techniques on reconfigurable SoCs to achieve low power consumption in image processing applications. DVS involves adjusting voltage levels dynamically based on performance needs, while DPR allows reconfiguring specific hardware regions without affecting the static part. Debugging support is integrated for hardware validation.
2：Sample Selection and Data Sources:
Image processing applications are used as case studies, with images of specific resolutions (e.g., 1920x1080 16-bit images for DVS, 256x256 RGB 32-bit images for DPR) processed. The TULIPP project provides a reference platform and guidelines.
3：List of Experimental Equipment and Materials:
ZC702 development board (Xilinx Zynq-7000 SoC), EMC2-Z7030 board (for DPR), FreeRTOS operating system, Xilinx SDSoC tools, custom SDSoC image processing library, power monitoring components (PMBus, I2C interface), and debugging tools (e.g., Integrated Logic Analyzers, serial communication).
4：Experimental Procedures and Operational Workflow:
For DVS, power monitoring and voltage scaling are controlled from the PS-side using FreeRTOS tasks; voltage levels are set dynamically, and power consumption is measured. For DPR, partial bitstreams are loaded from SD card, and reconfiguration is performed via PCAP; image processing functions (e.g., median filter, sepia filter) are swapped at runtime. Debugging involves data capture from trace buffers and transfer to a terminal for analysis.
5：Data Analysis Methods:
Power consumption is measured and compared across different voltage levels; execution times are recorded; resource utilization is analyzed using synthesis reports; debugging data is visualized with waveform viewers like GTKWave.
独家科研数据包，助您复现前沿成果，加速创新突破
获取完整内容
