- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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Single Flip-Chip Packaged Dielectric Resonator Antenna for CMOS Terahertz Antenna Array Gain Enhancement
摘要： A single dielectric resonator antenna (DRA) capable of enhancing the antenna gain of each element of a 2×2 THz antenna array realized in a 0.18-μm CMOS technology is proposed in this work. The DRA implemented in a low-cost integrated-passive-device (IPD) technology is flip-chip packaged onto the CMOS antenna array chip through low-loss gold bumps. By designing the DRA to work at the higher-order mode of TE3,δ,9, only single DRA instead of conventionally needing four DRAs is required to simultaneously improve the antenna gain of each element of the 2×2 antenna array. This not only simplifies the assembly process but it can also reduce the assembly cost. Moreover, the DRA can provide great antenna gain enhancement because of being made of high-resistivity silicon material and higher-order mode operation. The simulated antenna gain of each on-chip patch antenna of the 2×2 CMOS antenna array can be increased from 0.1 to 8.6 dBi at 339 GHz as the DRA is added. To characterize the proposed DRA, four identical power detectors (PDs) are designed and integrated with each element of the 2×2 THz antenna array, respectively. By measuring the voltage responsivity of each PD output, the characteristics of each antenna of the antenna array with the proposed DRA, including the gain enhancement level and radiation pattern, can be acquired. The measurement results follow well with the simulated ones, verifying the proposed DRA operation principle. The four PDs with the proposed DRA are also successfully employed to demonstrate a THz imaging system at 340 GHz. To the best of the authors’ knowledge, the proposed DRA is the one with the highest-order operation mode at THz frequencies reported thus far.
关键词： Silicon,Flip-chip packaging,Terahertz,CMOS,Terahertz imaging system,Antenna,Higher-order mode,Power detector,Dielectric resonator antenna
更新于2025-09-23 15:23:52
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[IEEE 2018 7th Electronic System-Integration Technology Conference (ESTC) - Dresden, Germany (2018.9.18-2018.9.21)] 2018 7th Electronic System-Integration Technology Conference (ESTC) - Integration with Light
摘要： This paper reports the use of Laser-induced Forward Transfer (LIFT) technology for printing of multilayer flexible circuitries and the fabrication of micro-bumps for flip-chip bonding of packaged LEDs and bare die microcomponents. Bonding of passive and functional surface mount devices (SMD) on low-temperature polyethylene terephthalate (PET) foils have been demonstrated using two selective bonding techniques. Firstly, using a high intensity near-infrared (NIR) lamp, a bare die NFC chip was bonded on micro-bumps formed with LIFT printed isotropic conductive adhesive (ICA) within less than a minute. Secondly, using a high intensity Xenon lamp, passive components and packaged LEDs were bonded within 5 seconds on micro-bumps formed with conventional Sn–Ag–Cu (SAC) lead-free alloys. In the both cases, due to selective light absorption, a limited temperature increase was observed in the PET substrates allowing successful bonding of components onto the delicate polyethylene foil substrates using conventional interconnect materials.
关键词： LIFT,low temperature bonding,NIR curing,conductive adhesive,lead-free SAC solder,photonic soldering,flip-chip bonding,laser printing
更新于2025-09-23 15:23:52
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Flip-Chip Integration of InP and SiN
摘要： We present an interface for hybrid flip-chip integration of InP based laser sources to silicon nitride based photonic platforms. The design enables efficient high optical power coupling over a wide temperature range. The optical modes of laser and SiN chip are expanded using integrated tapers allowing for high alignment tolerance. The chips comprise physical alignment stops for vertical alignment. In the horizontal direction, the integration interface is optimized for active and/or visual alignment with high precision using precise visual alignment marks. The hybrid integrated chip shows a waveguide coupled optical power of more than 40mW and can operate at elevated temperatures up to 85°C.
关键词： silicon photonics,silicon nitride,flip-chip,laser,hybrid integration
更新于2025-09-23 15:22:29
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[IEEE 2018 IEEE International Conference on Semiconductor Electronics (ICSE) - Kuala Lumpur (2018.8.15-2018.8.17)] 2018 IEEE International Conference on Semiconductor Electronics (ICSE) - Challenges in Developing Thin Profile, Smaller Flip Chip Bump Pitch FCBGA Packaging
摘要： The influence of substrate copper density distribution, substrate bump coplanarity, stiffener attach process, and substrate clamping by magnetic boat during die attach were evaluated. The substrate warpage behavior throughout the package assembly process was characterized using shadow moiré. Balanced substrate copper density distribution, pre-stiffener substrate before flip chip bump reflow, and substrate clamping during reflow reduced flip chip solder bridging fall-out. The decrease in solder bridging was due to the lower substrate warpage seen during die attach. In particular, solder bridging fall-out was well-correlated to die attach area warpage. Substrate with and without clamping during reflow has met the package reliability requirement.
关键词： Substrate Warpage,FCBGA,Smaller Pitch,Flip Chip Bump Solder Bridging
更新于2025-09-23 15:22:29
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Evidence of reversible oxidation at CuInSe <sub/>2</sub> grain boundaries
摘要： Silicon photonics leverages microelectronic fabrication facilities to achieve photonic circuits of unprecedented complexity and cost efficiency. This efficiency does not yet translate to optical packaging, however, which has not evolved substantially from legacy devices. To reach the potential of silicon photonics, we argue that disruptive advances in the packaging cost, scalability in the optical port count, and scalability in the manufacturing volume are required. To attain these, we establish a novel photonic packaging direction based on leveraging existing microelectronics packaging facilities. We demonstrate two approaches to fiber-to-chip interfacing and one to hybrid photonic integration involving direct flip-chip assembly of photonic dies. Self-alignment is used throughout to compensate for insufficient placement accuracy of high-throughput pick and place tools. We show a self-aligned peak transmission of –1.3 dB from standard cleaved fibers to chip and of –1.1 dB from chip to chip. The demonstrated approaches are meant to be universal by simultaneously allowing wide spectral bandwidth for coarse wavelength division multiplexing and large optical-port count.
关键词： flip-chip devices,optical fiber communication,Integrated optoelectronics,packaging,optical polymers
更新于2025-09-23 15:19:57
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Thin-film flip-chip UVB LEDs realized by electrochemical etching
摘要： We demonstrate a thin-?lm ?ip-chip (TFFC) light-emitting diode (LED) emitting in the ultraviolet B (UVB) at 311 nm, where substrate removal has been achieved by electrochemical etching of a sacri?cial Al0:37Ga0:63N layer. The electroluminescence spectrum of the TFFC LED corresponds well to the as-grown LED structure, showing no sign of degradation of structural and optical properties by electrochemical etching. This is achieved by a proper epitaxial design of the sacri?cial layer and the etch stop layers in relation to the LED structure and the electrochemical etch conditions. Enabling a TFFC UV LED is an important step toward improving the light extraction ef?ciency that limits the power conversion ef?ciency in AlGaN-based LEDs.
关键词： Thin-film flip-chip,AlGaN,light extraction efficiency,UVB LEDs,electrochemical etching
更新于2025-09-23 15:19:57
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Potential of Indium Plating Chemistry; インジウムめっきの可能性;
摘要： インジウムは 19 世紀後半から装飾用途および軸受用途として利用されてきたが，近年では化合物半導体，電極，液晶セル，はんだ，低融点合金など，電気?電子工業分野における利用が増加している。その中でも透明電極用 ITO（Indium Tin Oxide，酸化インジウムスズ）用途がインジウム需要の約 85% を占めている。めっき浴としては，電解めっきおよび無電解めっきに大別される。古くからインジウムおよびインジウム合金の様々の浴種の提案がされているが，近年では新規めっき浴の提案よりも，現行浴を用い，熱拡散や低融点を利用した検討が多い。今回，本稿ではインジウムの特性，用途，各種めっき液を簡単に紹介するとともに著者らが最近開発した技術についても紹介する。
关键词： Low Melting Point,Flip-Chip,Plating,Indium,Pb-Free
更新于2025-09-19 17:15:36
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[IEEE 2018 19th International Conference on Electronic Packaging Technology (ICEPT) - Shanghai (2018.8.8-2018.8.11)] 2018 19th International Conference on Electronic Packaging Technology (ICEPT) - Research and Introduction of the Process Flow of Full-automatic Wafer Level Flip Chip Machine
摘要： At present, there are many kinds of process technologies that can be used in the field of microelectronic packaging. Current mainstream technologies mainly include gate array package (BGA), flip chip technology (FC), chip scale package (CSP), system-in-package (SIP), and three-dimensional (3D) package. After years of development, flip chip technology has gradually developed into a mainstream technology in the field of electronic packaging. The biggest feature of the flip chip technology is that the interconnect line is short. Compared with other packaging methods, it has the characteristics of small area and high density, and the overall performance is better than other methods. In the context of flip chip technology, the development of its corresponding process equipment is particularly important for the improvement of the industry's capacity. However, at present in the Chinese domestic market, there are very few institutions and companies that conduct research on domestic wafer-level flip-chip equipment, and they have not achieved mass production. The device we developed is a non-lead bonded wafer level flip-chip soldering machine for IC semiconductor material packages. It uses heating, pressing, and ultrasonic energy modules to form electrical connections between the chip electrodes and the substrate. Solid-state soldering and packaging processes for IC integrated circuits and other products. It is also compatible with flip-chip soldering of 4-inch wafer substrates or ceramic substrates, 6-inch, 8-inch, and 12-inch wafer substrates. It contains four major systems: mechanical systems, electronic control systems, image recognition systems, and software systems. The mechanical system consists of a wafer ring loading and unloading module, a wafer table module, a flip chip module, a die bonding head module, a dispensing module, an ultrasonic and heating and pressing module, a wafer substrate table module and a wafer substrate automatic loading and unloading module. Each module works in coordination with each other. After the chip goes through the flip chip and the die bonder module from the wafer table, it is connected with the substrate after the ball bonding by the glue and other fillers. And is supplemented by hot pressing or ultrasonic waves is supplemented to strengthen connection performance. After the equipment is debugged, the time of the cycle can be used to measure the time period of the whole flip-chip solid crystal up to 1.8s. The results were observed under microscope, the positioning accuracy of flip-chip welding can reach 10μm. The appearance of this device will not only realize the industrialization of the flip-chip interconnection technology of the IC semiconductor industry, but its successful development is of great significance to the domestic development and manufacturing of semiconductor packaging equipment.
关键词： Flip chip,Microelectronics package,Positioning accuracy,Wafer level equipment
更新于2025-09-19 17:15:36
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[IEEE 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Las Vegas, NV, USA (2019.5.28-2019.5.31)] 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) - Vertical Laser Assisted Bonding for Advanced "3.5D" Chip Packaging
摘要： In this work the processes of laser assisted bonding (LAB) is compared to thermal compression bonding (TCB). Their respective advantages and disadvantages regarding the assembly of flip chip stacks are compared. It is found, that the LAB allows for faster processing, negligible compression force and creates less internal stress in the chip stack. The concept of “3.5D” stacking is introduced. This new concept allows for the vertical bonding of chips/semiconductors to the sides of a chip stack. The vertically bonded parts can be used to contact the layers, which eliminates the individual necessity for through silicon vias (TSVs).
关键词： 3D-packaging,Silicon interposer,Thermal compression bonding (TCB),Inter metallic phase (IMC-layer),Laser assisted bonding (LAB),System on Package (SOP),Laser beam modulation,vertical Flip Chip bonding
更新于2025-09-16 10:30:52
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Random Voids Generation and Effect of Thermal Shock Load on Mechanical Reliability of Light-Emitting Diode Flip Chip Solder Joints
摘要： To make the light-emitting diode (LED) more compact and effective, the flip chip solder joint is recommended in LED chip-scale packaging (CSP) with critical functions in mechanical support, heat dissipation, and electrical conductivity. However, the generation of voids always challenges the mechanical strength, thermal stability, and reliability of solder joints. This paper models the 3D random voids generation in the LED flip chip Sn96.5–Ag3.0–Cu0.5 (SAC305) solder joint, and investigates the effect of thermal shock load on its mechanical reliability with both simulations and experiments referring to the JEDEC thermal shock test standard (JESD22-A106B). The results reveal the following: (1) the void rate of the solder joint increases after thermal shock ageing, and its shear strength exponentially degrades; (2) the first principal stress of the solder joint is not obviously increased, however, if the through-hole voids emerged in the corner of solder joints, it will dramatically increase; (3) modelling of the fatigue failure of solder joint with randomly distributed voids utilizes the approximate model to estimate the lifetime, and the experimental results confirm that the absolute prediction error can be controlled around 2.84%.
关键词： randomly distributed voids,solder joint,flip chip,light-emitting diode,reliability
更新于2025-09-16 10:30:52