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[IEEE 2018 IEEE 15th International Conference on Group IV Photonics (GFP) - Cancun (2018.8.29-2018.8.31)] 2018 IEEE 15th International Conference on Group IV Photonics (GFP) - 20-Gb/s Silicon Optical Modulators for the 2 μm Wavelength Band
摘要： We demonstrate silicon-on-insulator based high speed modulators working at a wavelength of 1950 nm. The carrier-depletion Mach-Zehnder interferometer modulator operates at a data rate of 20 Gbit/s with an extinction ratio of 5.8 dB and modulation efficiency (VπLπ) of 2.68 Vcm at 4 V reverse bias.
关键词： high speed modulators,1950 nm,carrier-depletion,silicon-on-insulator,Mach-Zehnder interferometer
更新于2025-09-10 09:29:36
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Steep Slope Silicon-On-Insulator Feedback Field-Effect Transistor: Design and Performance Analysis
摘要： Feedback ?eld-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has conspicuous subthreshold slope (SS) properties, advanced research for structure and performance of it is lacking. In this paper, single-gated and spacer-less silicon-on-insulator (SOI) FBFET with extremely steep switching (～1 mV/decade) characteristic is studied in various aspects; SS attribute, performance variation of scaled FBFET, the impact of structural variation, the gate margin for the device layout, and the hysteresis window. The prospect of SOI FBFET as a future candidate for CMOS logic application is investigated in detail.
关键词： feedback ?eld-effect transistor (FBFET),gate switching and margin rate,silicon on insulator (SOI),Channel length variation
更新于2025-09-10 09:29:36
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Fully Depleted SOI Pixel Detector With Multijunction Structure in p-Type Substrate
摘要： A fully depleted silicon-on-insulator (SOI) pixel detector with multijunction structure in p-type substrate is proposed to reduce the diode capacitance and improve the effective shielding between the SOI circuits and sensor. A buried p-well (BPW) and a buried n-well (BNW) are applied to their respective bias voltages to shield SOI circuits from the sensor in the substrate. BPW is biased to counteract the back-gate effect. A deeply BPW is employed to form a potential barrier to electrons in BNW, stopping the front-to-back leakage current. Lateral electric field is also formed to accelerate holes to the p+ charge collector. The simulation results demonstrate that the pixel can achieve its objectives under a full depletion condition. The capacitance of the charge collector can be reduced, which depends primarily on the charge-collector/BNW junction.
关键词： fully depleted,Capacitance,silicon-on-insulator (SOI) pixel detector,crosstalk
更新于2025-09-10 09:29:36
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[IEEE 2018 IEEE International Conference on Semiconductor Electronics (ICSE) - Kuala Lumpur (2018.8.15-2018.8.17)] 2018 IEEE International Conference on Semiconductor Electronics (ICSE) - Characterization of SOI Film Thickness, Oxide Thickness and Charges with C-V Measurement
摘要： Capacitance-Voltage measurement is a crucial method to characterize and study the behavior of the device. In this work, the capacitance voltage characteristics of a partially depleted Silicon-On-Insulator MOSFET were analyzed and discussed. The important parameters like the gate oxide thickness, buried oxide thickness, silicon film thickness, fixed oxide charges and interface trapped charges were extracted from the capacitance voltage between the front gate and drain/source at different back gate voltage. The measured results were in good agreement with inline and XSEM result. The frequency dependency on the result is also observed and discussed in this paper.
关键词： Accumulation,Charges,Inversion,PD MOSFET,Silicon-On-Insulator,Depletion,C-V Characteristics
更新于2025-09-09 09:28:46
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The formation mechanism of globally biaxial strain in He <sup>+</sup> implanted silicon-on-insulator wafer based on the plastic deformation and smooth sliding of buried SiO <sub/>2</sub> film
摘要： In this paper, we proposed an approach to obtain a globally biaxially strained silicon-on-insulator (SOI) wafer, and the strain mechanism was discussed. By this process, both biaxially tensile and compressive strained SOI (sSOI) can be obtained. The strain introduced into the SOI layer is mainly contributed by the plastic deformation of the buried SiO2 film caused by annealing with the deposition of a high-stress SiN film. Furthermore, He+ implantation at the interface between SiO2 and the substrate Si layer is confirmed to effectively enhance the strain by the sliding of the buried SiO2 at the SiO2-substrate Si interface. Raman spectroscopy shows that the strain of the He+ implanted sSOI has a significant enhancement of more than 300% compared with the unimplanted sSOI.
关键词： silicon-on-insulator,biaxial strain,plastic deformation,He implantation,SiO2 film
更新于2025-09-09 09:28:46
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Synthesis Technique for Low-Loss mm-Wave T/R Combiners for TDD Front-Ends
摘要： A time-division duplex (TDD) transmit/receive (T/R) millimeter-wave (mm-wave) front-end comprises a power amplifier (PA), a low-noise amplifier (LNA), an antenna switch, and appropriate passive matching and combining networks. In this paper, a synthesis methodology is proposed that minimizes the overall losses by combining the PA output and the LNA input matching networks together with the T/R switch into one network. The technique improves mm-wave transceiver performance in terms of PA efficiency and LNA noise figure. The proposed T/R combiner can achieve high linearity and can handle large PA output voltage swings. The architecture can be implemented in any process which provides high integration capability. A Ka-band implementation is demonstrated using 45 nm CMOS silicon-on-insulator that includes a high power, four-stack-based PA and an inductively source-degenerated cascode-based LNA. Within the front-end, the PA achieves saturated output power of 23.6 dBm with peak power added efficiency of 28%, while the LNA achieves NF of 3.2 dB. The overall chip area is 0.54 mm2, including pads.
关键词： transmit/receive (T/R) switch,low-noise amplifier (LNA),power amplifier (PA),5G transmitters,stacked power amplifier,silicon-on-insulator (SOI),time-division duplex (TDD),CMOS,millimeter-wave (mm-wave),Ka-band
更新于2025-09-04 15:30:14
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Quarter Video Graphics Array Digital Pixel Image Sensing With a Linear and Wide-Dynamic-Range Response by Using Pixel-Wise 3-D Integration
摘要： We have developed a quarter video graphics array (QVGA) digital pixel image sensor by using the 3-D integration technology. The pulse-frequency modulation (PFM) analog-to-digital converter (ADC) operates as a digital pixel, which overcomes the signal saturation due to the full well capacity of the photodiode (PD). We have also newly designed a PFM-ADC for pixels with a pinned PD and a floating diffusion to comply with the CMOS image sensor process used to attain high sensitivity and low noise. PDs, comparators, logic circuits, and counters are integrated into two silicon-on-insulator layers by pixel-wise 3-D integration with gold electrodes with a 5 μm diameter, thereby achieving a QVGA resolution for a 20-mm square chip in the 0.18- and 0.2-μm process nodes. The developed sensor exhibits both the excellent linearity and a wide-dynamic range of more than 96 dB. Video images with a high bit depth of 16 bit are also obtained to demonstrate the superior image sensing, capable of capturing the real world at high fidelity.
关键词： analog-to-digital converters (ADCs),dynamic range,image sensors,3-D integrated circuits,integrated circuit interconnections,pulse generation,silicon on insulator (SOI)
更新于2025-09-04 15:30:14