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[IEEE 2019 IEEE 5th International Conference for Convergence in Technology (I2CT) - Bombay, India (2019.3.29-2019.3.31)] 2019 IEEE 5th International Conference for Convergence in Technology (I2CT) - Multiplexer based Voltage Controlled Delay Buffer Element
摘要： This paper presents a voltage controlled delay buffer using a 2:1 multiplexer, designed in 0.35 μm CMOS process. The multiplexer is realized with transmission gate, which results in achievement of high speed, low power and full swing output characteristics of delay buffer. The least attained post layout rising edge delay is 120 ps that is comparable with standard cell inverter. The delay regulation range achieved over control voltage of 0 V to 3.3 V is from 120ps to 560ps. The performance of delay buffer for single edge delay control across PVT variations is successfully verified by design of modified delay lock loop.
关键词： Process Voltage and Temperature (PVT),Current Starved Inverter,Time-to-Digital Converter (TDC),Delay Lock Loop (DLL)
更新于2025-09-23 15:21:01
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Autonomous Path Planning by Unmanned Aerial Vehicle (UAV) for Precise Monitoring of Large-Scale PV plants
摘要： This paper presents a 3.6 GHz low-noise fractional-N digital phase-locked loop (PLL) that achieves low in-band phase noise. Phase detection is carried out by a proposed 10-bit, 0.8 ps resolution time-to-digital converter (TDC) using a charge pump and a successive-approximation-register analog-to-digital converter (SAR-ADC) with low power and small area. The latency of the TDC is addressed by the designed building blocks. The fractional spurs are reduced by dual-loop least-mean-square (LMS) calibration. A (cid:2)(cid:3)-less and MOS varactor-less LC digitally-controlled oscillator (DCO) is proposed whose frequency resolution is enhanced to 7 kHz (or a unit variable capacitance of 2.6 aF) using a bridging capacitor technique. A prototype chip is fabricated using a 65 nm CMOS process, occupying an active area of 0.38 mm2 and consuming a power of 9.7 mW at a reference frequency of 50 MHz. The measured in-band phase noise is 107.8 dBc/Hz to 110.0 dBc/Hz with a loop bandwidth of 1 to 5 MHz.
关键词： digitally controlled oscillator (DCO),least-mean-square (LMS),digital phase-locked-loop (PLL),time-to-digital converter (TDC),successive-approximation-register analog-to-digital converter (SAR-ADC),frequency synthesizer,CMOS,sub-picosecond resolution
更新于2025-09-23 15:19:57
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A Design of 6.8 mW All Digital Delay Locked Loop With Digitally Controlled Dither Cancellation for TDC in Ranging Sensor
摘要： This paper presents a design of 6.8 mW all digital delay locked loop (ADDLL) with digitally controlled dither cancellation (DCDC) for time to digital converter (TDC) in ranging sensors. ADDLL uses the accumulator (ACC) to control the delay of digitally controlled delay line (DCDL) during phase locking which utilizes less power and area as compared to analog delay locked loop (DLL). In the lock state, the ACC value dithers due to the closed loop operation. A digital controller is proposed to detect the lock state, performs dither cancelation and selects the optimum ACC value for controlling the delay of the replica DCDL for TDC operation. It helps the jitter reduction in the ADDLL. Additionally, it provides robustness against glitches, false locking and unlocking in a noisy environment. The ADDLL peak to peak jitter and RMS jitter at 625 MHz are 6.5 ps and 1.2 ps respectively. The ADDLL including DCDC is implemented on 0.18 μm CMOS technology with an operational range of 350～900 MHz. It consumes only 6.8 mW at 625 MHz power with 1.8 V power supply. The area utilization is 0.06 mm2.
关键词： digital controller,time to digital converter (TDC),jitter,All digital delay locked loop (ADDLL),light detection and ranging (LIDAR)
更新于2025-09-19 17:13:59
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An IR-UWB Angle-of-Arrival Sensor IC Using Auto-Toggled Time-to-Digital Converter
摘要： This letter introduces an impulse radio-ultrawideband (IR-UWB) angle-of-arrival (AoA) sensor integrated circuit (IC) using an auto-toggled time-to-digital converter (TDC). The detectable range of the proposed AoA sensor can be extended by a factor of 2 by utilizing an auto-toggle operation that toggles the TDC’s input signal according to the target’s position. The analog front end (AFE) of the receivers is designed with a 3–5 GHz band and the system comprises two AFEs and one digital back end (DBE). The proposed IR-UWB AoA sensor IC was fabricated using a 65-nm CMOS process. The measurable angular range was ± 40?, and an angle error of ± 1.5? was measured.
关键词： impulse radio-ultrawideband (IR-UWB),time-to-digital converter (TDC) with auto-toggle,Angle-of-arrival (AoA)
更新于2025-09-11 14:15:04