研究目的
Investigating the design and performance of a 3.6 GHz low-noise fractional-N digital PLL using a SAR-ADC-based TDC for achieving low in-band phase noise.
研究成果
The paper demonstrates a high-performance digital PLL with a practically designed TDC and DCO, achieving competitive in-band phase noise, low power, and small area. It concludes with the successful demonstration of a 3.6 GHz low-noise fractional-N digital PLL using the proposed TDC and DCO.
研究不足
The paper mentions issues with on-chip grounding, single-ended structure of the output buffer, and parasitic inductance in the bond wire affecting noise and spur performance. It also notes the challenge of improving TDC's linearity or removing spur as a future research target.
1：Experimental Design and Method Selection:
The paper describes the design of a fractional-N digital PLL with a focus on achieving low in-band phase noise using a proposed TDC and DCO.
2：Sample Selection and Data Sources:
A prototype chip is fabricated using a 65 nm CMOS process.
3：List of Experimental Equipment and Materials:
The TDC uses a charge pump and SAR-ADC, and the DCO is implemented with MOM capacitors.
4：Experimental Procedures and Operational Workflow:
The paper details the design of building blocks to address TDC latency and gain mismatch, and the use of dual-loop LMS calibration to reduce fractional spurs.
5：Data Analysis Methods:
The performance is evaluated based on phase noise measurements and power consumption.
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